Regenerative comparator with floating capacitor for energy‐harvesting applications

Abstract

An energy-efficient regenerative comparator design is unveiled. A floating capacitor is utilized to protect the complete discharge of the preamplifier output nodes by NMOS input transistors. The introduced floating capacitor is flipped around the preamplifier to allow PMOS cross-couple transistor charge reutilization and elevate amplification gain at the integration phase. By increasing amplification gain, the input common mode voltage of the NMOS latch that is toggled within some delay is increased, too. Therefore, the latch stage is activated strongly, and regeneration delay is reduced. Simulation results corroborate that the proposed technique reduces power consumption and input-referred offset by more than 60% compared with results of similar previous works. Furthermore, the referred noise and delay are improved more than 30%.

A low settling time switching scheme for SAR ADCs with reset‐free regenerative comparator

“…Designing a low-power comparator is paramount for SAR ADCs since ncomparisons need to be performed for an n-bit ADC. 26,27 The schematic of the conventional single-ended regenerative comparator, alongside its simulated waveforms, is shown in Figure 5. The tail transistor (M t1 ) as a current source reduces dynamic offset voltage by constraining current flow from Vdd.…”

“…Regenerative comparators are spotted for excellent power efficiency by omitting static currents and are widely used class of comparators in many applications. Designing a low‐power comparator is paramount for SAR ADCs since n‐comparisons need to be performed for an n‐bit ADC 26,27 . The schematic of the conventional single‐ended regenerative comparator, alongside its simulated waveforms, is shown in Figure 5.…”

“…Incomplete discharging of the preamplifier output nodes ( / ) improves regeneration speed of the NMOS latch. The regeneration delay can be written as 26 : is the input differential voltage of the latch stage, is transconductance of back to back inverter, and is output capacitive load of the latch stage. Since can be doubled by the proposed technique, the latch regeneration time can be reduced.…”