Summary This paper unveils two efficient free running (FR) quenching circuits with the aim of reducing quenching time (QT) to minimize avalanche charge. Likewise, one circuit is compactly designed with low power consumption, suitable for single‐photon avalanche diode (SPAD) with hold‐off time below 10 ns. In second circuit, tunable hold‐off and reset‐time are provided within a wide range without decreasing QT, which are desirable in many applications. Proper operation and circuit uncertainty is assessed by Monte Carlo analysis in a standard 90‐nm complementary metal‐oxide semiconductor (CMOS) technology. In a bid to do a comparison between previously reported circuits and the proposed circuits, they are simulated with same SPAD model and parameters and results corroborate the proposed circuits guarantee active quenching time (AQT) of below 1 ns. Proposed circuits with current and area consumption of 0.74 μA, 32 μm2 for 7‐ns dead time and 16.2 μA, 93 μm2 for 21‐ns dead time are more efficient in terms of QT, area, and power consumption in comparison with other works.

An energy-efficient regenerative comparator design is unveiled. A floating capacitor is utilized to protect the complete discharge of the preamplifier output nodes by NMOS input transistors. The introduced floating capacitor is flipped around the preamplifier to allow PMOS cross-couple transistor charge reutilization and elevate amplification gain at the integration phase. By increasing amplification gain, the input common mode voltage of the NMOS latch that is toggled within some delay is increased, too. Therefore, the latch stage is activated strongly, and regeneration delay is reduced. Simulation results corroborate that the proposed technique reduces power consumption and input-referred offset by more than 60% compared with results of similar previous works. Furthermore, the referred noise and delay are improved more than 30%.

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Summary This paper presents an energy‐efficient fully differential switching scheme for successive approximation register (SAR) analog‐to‐digital converters (ADCs). During the sampling phase, the top and bottom plates of all capacitors except most significant bit (MSB) capacitors are grounded in digital‐to‐analog converter (DAC) arrays. The input signals are bottom plate sampled on MSB capacitors. This technique can reduce the settling time by more than 87.5% in comparison with the conventional switching scheme. Furthermore, a novel reset‐free regenerative comparator is unveiled in this paper. The proposed comparator is armed to amplify its inputs both during the reset and evaluation phases. In comparison with a conventional single‐ended comparator, the proposed comparator can reduce power consumption above 90% for the almost same input‐referred offset voltage. The proposed scheme is designed with a resolution of 8‐bit and a sampling rate of 90 MS/s in a standard 65‐nm CMOS technology. The simulation results certify that the ADC dissipates 363‐μW power with a 1.2‐V supply voltage and achieves a 7.13 effective number of bits (ENOBs), yielding a 28.8 fJ/conversion step Nyquist rate Walden FOM.

A low voltage two-stage rail-to-rail regenerative comparator is presented. For the first time, a thyristor-based latch is introduced in this work, enabling the comparator’s rail-to-rail operation. The proposed comparator is post-layout simulated in a standard 180nm CMOS technology. The results certify that the comparator’s delay and power are less than 28ns and 230nW with 0.6V supply voltage and 1MHz sample rate. The total input-referred offset voltage (3std+mean) is less than 6.2mV over the entire rail-to-rail common-mode voltage range. In comparison with similar works the proposed comparator has the lowest delay and offset and achieves the best FOM.