Design and analysis of a high speed double-tail comparator with isomorphic latch-preamplifier pairs and tail bootstrapping

Rahmani, S.; Ghaznavi‐Ghoushchi, M. B.

doi:10.1007/s10470-017-1048-6

Cited by 9 publications

(9 citation statements)

References 11 publications

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“…Table 7 gives details regarding the comparison on the basis of power consumption of this comparator with other pertinent associated studies. [32] 130 nm 1.0 V 130 nm 100 µW [33] 180 nm 1.1 V -180 nm 1300 µW [34] 180 nm --180 nm ∼ =750 µW [35] 65 nm 1.2 V -65 nm 2800 µW [36] 65 nm 1.2 V 65 nm 370 µW [37] 180 nm 0.7 V to 1.1 V 180 nm 420 µW GB-CMFD (Proposed-architecture) 90 nm 0.7 V 839 V/µs 90 nm 362 µW…”

Section: Discussionmentioning

confidence: 99%

An Improved CMOS Design of Op-Amp Comparator with Gain Boosting Technique for Data Converter Circuits

Khatak

Kumar

Dhull

2018

JLPEA

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A modified architecture of a comparator to achieve high slew rate and boosted gain with an improvement in gain design error is introduced and investigated in this manuscript. It employs the conventional architecture of common-mode current feedback with the modified gain booster topology to increase gain, slew rate, and reduced gain error from the conventional structure. Observation from the simulation results concludes that the modified structure using 24 transistors shows power dissipation of 362.29 μW in 90 nm CMOS technology by deploying a supply voltage of 0.7 V, which is a 70% reduction as compared to the usual common mode feedback (CMFD) structure. The symmetric slew rate of 839.99 V/µs for both charging and discharging is obtained, which is 173% more than the standard CMFD structure. A reduction of 0.61% in gain error is achieved through this architecture. A SPICE simulation tool based on 90 nm CMOS technology is employed for executing the Monte Carlo simulations. A brief comparison with earlier CMFD structures shows improved performance parameters in terms of power consumption and slew rate with the reduction in gain error.

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Section: Discussionmentioning

confidence: 99%

An Improved CMOS Design of Op-Amp Comparator with Gain Boosting Technique for Data Converter Circuits

Khatak

Kumar

Dhull

2018

JLPEA

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“…Applications such as RF receiver and data converters have power dissipation as bottle neck hence use of comparator for such design needed to exercised due caution. The need for power reduction has opened the circuit design to look for topology such as dynamic comparator [2], [3], [4], [5], [6].…”

Section: Introductionmentioning

confidence: 99%

A Low Input Referred Noise Dynamic Comparator for High Speed Applications

2019

IJRTE

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“…In [1,[8][9][10][11][12][13][14] and [26][27][28], the positive feedback circuit has been added to the core body of the pre-amplifier stage to significantly reduce the comparator response time (delay). However, the positive feedback circuit itself increases both the power consumption as well as the input-referred noise [1].…”

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confidence: 99%

“…However, due to the disadvantages of the conventional dynamic comparators including: high delay, high dynamic power consumption and input-referred voltage errors; the designers have led to the development of the modified double-tail dynamic comparators [5]. However, in order to improve the speed/accuracy trade-off of low-power ADCs, the improvement in the speed performance and power consumption of the double-tail dynamic comparators has drawn the most attention of the analogue integrated circuits designers [11][12][13][14][15]. In the recent years, various approaches have been discussed in [16][17][18][19][20][21][22][23], to improve the input offset performance of the comparators.…”

mentioning

confidence: 99%

“…For example, in [1], two transistors are utilised in series with the input differential pair as control switches in the pre-amplifier stage, to control the power consumption of the circuit. However, a larger chip area, incapability to operate in low supply voltages, and high input-referred noise due to the use of positive feedback block in the pre-amplifier stage, are the major disadvantages of the designs reported in [1,[8][9][10][11][12][13][14]. On the other hand, realising the integrated circuits in the subthreshold region and bulk-drive techniques are the main two approaches that significantly reduce the power consumption, while increase in the delay of the circuit can be considered as a reduction in the speed performance.…”

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confidence: 99%

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An energy‐efficient dynamic comparator in Carbon Nanotube Field Effect Transistor technology for successive approximation register ADC applications

Mahmoodian

Dolatshahi

Zanjani

et al. 2022

IET Circuits, Devices & Syst

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In this paper, a latch‐based energy‐efficient dynamic comparator is presented in Carbon Nanotube Field Effect Transistor (CNTFET) technology. The proposed comparator consists of two main stages: pre‐amplifier and latch. The latch stage is designed for the main purpose of low‐power consumption and high‐speed performances. The proposed speed‐up technique for the latch structure controls the threshold voltage (Vth) of the cross‐coupled inverters. So, the delay of the latch stage decreases and consequently, the overall delay of the comparator circuit is also reduced up to 19.4% while the maximum speed performance of the proposed comparator increases by 54% compared to the conventional double‐tail dynamic comparator. Additionally, the use of the proposed distinctive structure for the tail transistors in the latch stage, leads to more than 11% reduction in the energy per conversion of the proposed circuit compared to the conventional double‐tail dynamic comparator. To verify the circuit performances, the comparator circuit is simulated in HSPICE using 32 nm CNTFET Stanford model technology parameters. The simulation results show that the proposed comparator with the proposed speed‐up approach can operate up to 14.2 GHz with a sensitivity of 30 μV at the supply voltage of 1 V, while consumes only 42.38 μW of power. Therefore, the proposed comparator can be used in high‐resolution (up to 12 bit) and high‐speed low‐power analogue‐to‐digital converter applications. Moreover, the effects of the non‐ideal fabrication process (including the pitch and the threshold voltage variations), supply voltage and temperature variations are investigated in this work. Monte‐Carlo analysis shows that the standard deviation of the offset voltage is approximately 1.24 mV. Finally, the kickback noise of the proposed comparator is obtained as 80 μV, which shows the proper performance of the proposed comparator circuit in comparison with other reported designs.

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Design and analysis of a high speed double-tail comparator with isomorphic latch-preamplifier pairs and tail bootstrapping

Cited by 9 publications

References 11 publications

An Improved CMOS Design of Op-Amp Comparator with Gain Boosting Technique for Data Converter Circuits

An Improved CMOS Design of Op-Amp Comparator with Gain Boosting Technique for Data Converter Circuits

A Low Input Referred Noise Dynamic Comparator for High Speed Applications

An energy‐efficient dynamic comparator in Carbon Nanotube Field Effect Transistor technology for successive approximation register ADC applications

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