SPARC64: a 64-b 64-active-instruction out-of-order-execution MCM processor

Williams, Ted E.; Patkar, N.; Shen, Guanhao

doi:10.1109/4.475709

Cited by 25 publications

(4 citation statements)

References 7 publications

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“…We chose this model for its scalability and logical simplicity. In terms of dissipated energy it is comparable to the reservation station model [55,99], used in other high performance out-of-order processors such as Intel Pentium Pro [31], PowerPC [24], and SPARC64 [119,3].…”

Section: Key Power Consumers In Superscalar Micro-architecturementioning

confidence: 99%

Inherently lower-power high-performance superscalar architectures

Zyuban

Kogge

2001

IEEE Trans. Comput.

113

121

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Victor V. Zyuban When it comes to performance, modern computer design has become a well structured art which starts with instruction sets that maximize opportunities for concurrency, follows through with fast organizational techniques such as pipelining and super scalar execution, and ends with clever macro and circuit designs that are based on inherently fast CMOS fabrication technologies. When it comes to low power, however, exactly the opposite is true. Current techniques start with lowering supply voltages and making process changes to minimize capacitance, followed by some relatively simple techniques for minimizing power for particular logic macros, and then utilizing relatively ad hoc techniques, such as 'sleep modes', at higher levels. This work attempts to reverse this by bringing the power issue to the earliest phase of high-performance microprocessor development. We propose a methodology for power-optimization of high-performance microprocessors at the microarchitecture level. In particular, our work explores solutions to the problem that do not compromise performance. First, major targets for power reduction are identified within microarchitecture, where power is heavily consumed, or will be heavily consumed in next-generation processors. This involves developing energy models for structures where power grows with increasing issue width, such as Register File, Issue Window, Memory Disambiguation Unit, etc. Then, a multicluster microar-CHAPTER 6: IMPLEMENTATION OF THE ENERGY-EFFICIENT MULTI-CLUSTER ARCHITECTURE .

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Section: Key Power Consumers In Superscalar Micro-architecturementioning

confidence: 99%

Inherently lower-power high-performance superscalar architectures

Zyuban

Kogge

2001

IEEE Trans. Comput.

113

121

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“…This divider, implemented in a 1.2mm CMOS technology, is able to produce a 54-b result in 45 to 160ns, depending upon the particular data operands. The Hal SPARC V9 microprocessor, the Sparc64, also implements a version of this self-timed divider, producing IEEE double precision results in about seven cycles [52].…”

Section: Self-timingmentioning

confidence: 99%

Division algorithms and implementations

Obermann

Flynn

1997

IEEE Trans. Comput.

266

108

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Many algorithms have been developed for implementing division in hardware. These algorithms differ in many aspects, including quotient convergence rate, fundamental hardware primitives, and mathematical formulations. This paper presents a taxonomy of division algorithms which classifies the algorithms based upon their hardware implementations and impact on system design. Division algorithms can be divided into five classes: digit recurrence, functional iteration, very high radix, table look-up, and variable latency. Many practical division algorithms are hybrids of several of these classes. These algorithms are explained and compared in this work. It is found that, for low-cost implementations where chip area must be minimized, digit recurrence algorithms are suitable. An implementation of division by functional iteration can provide the lowest latency for typical multiplier latencies. Variable latency algorithms show promise for simultaneously minimizing average latency while also minimizing area.

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“…He applied this technique to a self-timed 160ns 54-bit mantissa divider [75] as a part of a floating-point divider. This design was incorporated in a commercial microprocessor design [73].…”

Section: Iterative Structuresmentioning

confidence: 99%