This study demonstrates the involvement of the MT2 (Mel1b) melatonin receptor in mediating phase advances of circadian activity rhythms by melatonin. In situ hybridization histochemistry with digoxigenin-labeled oligonucleotide probes revealed for the first time the expression of mt1 and MT2 melatonin receptor mRNA within the suprachiasmatic nucleus of the C3H/HeN mouse. Melatonin (0.9 to 30 microg/mouse, s.c.) administration during 3 days at the end of the subjective day (CT 10) to C3H/HeN mice kept in constant dark phase advanced circadian rhythms of wheel running activity in a dose-dependent manner [EC50=0.72 microg/mouse; 0.98+/-0.08 h (n=15) maximal advance at 9 microg/mouse]. Neither the selective MT2 melatonin receptor antagonists 4P-ADOT and 4P-PDOT (90 microg/mouse, s.c.) nor luzindole (300 microg/mouse, s.c.), which shows 25-fold higher affinity for the MT2 than the mt1 subtype, affected the phase of circadian activity rhythms when given alone at CT 10. All three antagonists, however, shifted to the right the dose-response curve to melatonin, as they significantly reduced the phase shifting effects of 0.9 and 3 microg melatonin. This is the first study to demonstrate that melatonin phase advances circadian rhythms by activation of a membrane-bound melatonin receptor and strongly suggests that this effect is mediated through the MT2 melatonin receptor subtype within the circadian timing system. We conclude that the MT2 melatonin receptor subtype is a novel therapeutic target for the development of subtype-selective analogs for the treatment of circadian sleep and mood-related disorders.

We introduce a new design style called extended burst-mode. The extended burst-mode design style covers a wide spectrum of sequential circuits ranging from delay-insensitive to synchronous. We can synthesize multiple-input change asynchronous finite state machines and many circuits that fall in the gray area (hard to classify as synchronous or asynchronous) which are difficult or impossible to synthesize automatically using existing methods. Our implementation of extended burstmode machines uses standard CMOS logic, generates low-latency outputs, and guarantees freedom from hazards at the gate level. In Part I, we formally define the extended burst-mode specification, provide an overview of the synthesis methods, and describe the hazard-free synthesis requirements for two different next-state logic synthesis methods: two-level sums-of-products implementation and generalized C-elements implementation. We also present an extension to existing theories for hazard-free combinational synthesis to handle nonmonotonic input changes.

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This paper describes an investigation of potential advantages and pitfalls of applying an asynchronous design methodology to an advanced microprocessor architecture. A prototype complex instruction set length decoding and steering unit was implemented using self-timed circuits. [The Revolving Asynchronous Pentium ® Processor Instruction Decoder (RAPPID) design implemented the complete Pentium II ® 32-bit MMX instruction set.] The prototype chip was fabricated on a 0.25-CMOS process and tested successfully. Results show significant advantages-in particular, performance of 2.5-4.5 instructions per nanosecond-with manageable risks using this design technology. The prototype achieves three times the throughput and half the latency, dissipating only half the power and requiring about the same area as the fastest commercial 400-MHz clocked circuit fabricated on the same process.

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This paper describes an investigation of potential advantages and risks of applying an aggressive asynchronous design methodology to Intel Architecture. RAPPID ("Revolving Asynchronous Pentium® Processor Instruction Decoder"), a prototype IA32 instruction length decoding and steering unit, was implemented using self-timed techniques. RAPPID chip was fabricated on a 0.25µ CMOS process and tested successfully. Results show significant advantages-in particular, performance of 2.5-4.5 instructions/nS-with manageable risks using this design technology. RAPPID achieves three times the throughput and half the latency, dissipating only half the power and requiring about the same area as an existing 400MHz clocked circuit.

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