Division algorithms and implementations

Obermann, S.F.; Flynn, Michael J.

doi:10.1109/12.609274

Cited by 266 publications

(115 citation statements)

References 46 publications

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“…To implement (3), a division block is necessary. The division module is built based on Newton-Raphson algorithm [12,13], which is briefly described here. NewtonRaphson division is a division method using functional iteration.…”

Section: Methodsmentioning

confidence: 99%

A continuous-time delta-sigma ADC with integrated digital background calibration

Tan

Miao

Palm

et al. 2016

Analog Integr Circ Sig Process

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This work presents a digital calibration technique in continuous-time (CT) delta-sigma (DR) analog to digital converter. The converter is clocked at 144 MHz with a low oversampling ratio (OSR) of only 8. Dynamic element matching is not efficient to linearize the digital to analog converter (DAC) when the OSR is very low. Therefore, non-idealities in the outermost multi-bit feedback DAC are measured and then removed in the background by a digital circuit. A third-order, four-bit feedback, single-loop CT DR converter with digital background calibration circuit has been designed, simulated and implemented in 65 nm CMOS process. The maximum simulated signal-to-noise and distortion ratio is 67.1 dB within 9 MHz bandwidth.

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Section: Methodsmentioning

confidence: 99%

A continuous-time delta-sigma ADC with integrated digital background calibration

Tan

Miao

Palm

et al. 2016

Analog Integr Circ Sig Process

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“…Muchas de las implementaciones prácticas están basadas en combinaciones de varios métodos. Por ejemplo, en la operación del cálculo del recíproco implementada en el microprocesador AMD-K7 [15], primero se parte de un valor inicial (semilla) almacenado en una LUT, este valor es almacenado con una precisión de pocos bits, y posteriormente mediante un algoritmo basado en iteración de funciones se obtiene el valor del recíproco aproximado a la precisión pedida, de esta manera se mejora la velocidad de convergencia hacia el resultado.…”

Section:  Precisiónunclassified

Implementaciones de Funciones Elementales en Dispositivos FPGA

Mazon¹

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In this thesis we have designed several hardware architectures of some typical digital subsystems for high performance communications systems, aiming at optimized implementations for these systems. The work has focused on two areas: the approximation of elementary functions, specifically the logarithm and arctangent, and the design of an emulator of additive Gaussian noise channel. The architectures have been designed at all times with the objective to achieve an efficient implementation in Field Programmable Gate Arrays devices (FPGAs), due to its increasing use in digital high performance communications systems. For the approximation of logarithm we have proposed two different architectures, one based on the use of multipartite table methods and the other based on the Mitchell's approximation with two correction stages: a piecewise linear interpolation with power-of-two slopes and truncated mantissa, and a LUT-based correction stage that corrects the piecewise interpolation error. A first architecture for the approximation of atan(y/x) is based on the computation of the reciprocal of x and the arctangent approximation, using multipartite Look-up tables (LUTs). This proposal reduces the power consumption compared to the best techniques described in the literature, such based on CORDIC. A second strategy for the approximation of atan(y/x) is based on logarithmic transformations, which transforms the calculation of the division of two inputs in a simple subtraction and requires the computation of atan(2 w ). This second strategy has resulted in two architectures, a first in which both the logarithm and atan(2 w ) have been implemented using multipartite LUTs, also combined with the use of non-uniform segmentation techniques in the calculation of atan(2 w ), and a second architecture using a piecewise linear interpolation with power-of-two slopes and correction tables. The results obtained with this strategy improve the first architecture discussed. Two architectures for the approximation of arctangent and one for the logarithm have resulted in three publications in internationals journals. We also have proposed several architectures for a Gaussian white noise generator. The designs are based on the Inversion method, specifically approximating the inverse of cumulative distributions functions by polynomial interpolation and non-uniform segmentation. These architectures offer its output a standard deviation of ±13.1σ and 13 fractional bits, higher values than practically all hardware generators present in the literature, employing, in comparison, fewer FPGA resources. Compared to Gaussian channel implementations based on the inversion method presented by other authors, our architectures achieve a significant reduction in area partially or completely eliminating the barrel-shifter. The results for Gaussian channel emulator have been sent to an international journal, being currently under review process.

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“…We use SRT dividers to obtain Q\s because of the possibility of achieving the desired area-speed tradeoff by a proper choice of Radix [4,11,2,8]. The important properties of SRT division are given in this section.…”

Section: Srt Dividersmentioning

confidence: 99%

“…Several modifications ranging from usage of higher radix to overlapped implementation have been proposed to increase the speed at the cost of area [11,8]. However, there is a limit on the maximum achievable throughput.…”

Section: Introductionmentioning

confidence: 99%