Source/drain extension region engineering in nanoscale double gate SOI MOSFETs: Novel design methodology for low-voltage analog applications

How crucial is back gate misalignment/oversize in double gate MOSFETs for ultra-low-voltage analog/rf applications?

“…1b) was modeled using the expression N SD (x) = (N SD ) peak exp(-x 2 /r 2 ), where (N SD ) peak is the peak S/D doping, r (lateral straggle) defines the roll-off [13][14][15][16][17][18] of the Gaussian S/D profile as ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2sd=lnð10Þ p , s is the spacer width. The S/D doping gradient (d) which provides a measure of lateral doping abruptness was evaluated as (d = 1/|dN SD (x)/dx|) [13][14][15][16][17][18][19] at the front gate edge and was varied from 3 to 5 nm/decade. Lower d values represent a steeper doping gradient, whereas higher values signify a gradual S/D junction.…”

“…9a, the most significant aspect of S/D profile engineering is the substantial improvement in V EA in Early voltage (V EA = I ds /g ds ) with an increase in r. Due to an increase in r, reduction in the net dopant concentration at the gate edge causes a significant reduction in the peak electric field [19], thus yielding higher values of V EA . S/D extension region engineering results in significant relative improvement in V EA by a factor of $4 for r > 10 nm.…”

“…In this work, we propose a design methodology to alleviate the above two critical issues for ultra-low-voltage (ULV) analog/rf devices operating in the subthreshold and low moderate inversion regions. We use the concept of gate-underlap design which has been studied extensively for digital [12][13][14][15][16][17][18] and analog/rf [19][20][21][22][23] applications. In high-volume manufacturing, gate-source/drain underlap devices were 'accidentally' fabricated in 0.35 micron CMOS technology [24].…”

FinFET SRAM Cells with Asymmetrical Bitline Access Transistors for Enhanced Read Stability

“…10. The underlap on the right side is longer as compared to the left side in an asymmetric FinFET-Asym2 [14]. When the voltage level of the left terminal of FinFET-Asym2 is higher than the right terminal, the on-current flowing from the left side of the device to the right side (I LR ) is reduced due to the increased series resistance of the channel with the longer underlap region on the right side of the device.…”

Design considerations of source and drain regions in nano double gate MOSFETs

“…To study the source/drain engineered nanoscale double gate MOSFETs, researchers often investigate Schottky barrier source/drain [4][5][6][7] and source/drain extension region [8][9][10]. However for the first time in this work, we have studied novel attributes and design considerations of the source and drain parameters in double gate MOSFETs using two-dimensional full quantum simulation.…”