FinFET SRAM Cells with Asymmetrical Bitline Access Transistors for Enhanced Read Stability

Abstract

Degraded data stability, weaker write ability, and increased leakage power consumption are the primary concerns in scaled static random-access memory (SRAM) circuits. Two new SRAM cells are proposed in this paper for achieving enhanced read data stability and lower leakage power consumption in memory circuits. The bitline access transistors are asymmetrically gate-underlapped in the proposed SRAM cells. The strengths of the asymmetric bitline access transistors are weakened during read operations and enhanced during write operations, as the direction of current flow is reversed. With the proposed hybrid asymmetric SRAM cells, the read data stability is enhanced by up to 71.6% and leakage power consumption is suppressed up to 15.5%, while displaying similar write voltage margin and maintaining identical silicon area as compared to the conventional memory cells in a 15 nm FinFET technology. Keywords

A 9T FinFET SRAM cell for ultra-low power application in the subthreshold regime

“…FinFET SRAM with minimum variatins and improved stability has been proposed in [18]. Finfet SRM with asymmetrical bitlines has been proposed in [19].…”

Dual Port 8T SRAM Cell Using FinFET & CMOS Logic for Leakage Reduction and Enhanced Read & Write Stability

“…In the shorted gate, both the gates are shorted and connected with the same voltage. In independent-gate (IG) FinFET in which the upper portion of the gate region is etched out to form a double gate, which can be biased separately [31,32]. For both the gate terminals can be biased independently, the IG FinFET exhibits more design flexibility.…”