Dual Port 8T SRAM Cell Using FinFET &amp; CMOS Logic for Leakage Reduction and Enhanced Read &amp; Write Stability

Duari, Chusen; Birla, Shilpi; Singh, A.K.

doi:10.29292/jics.v15i2.140

Cited by 10 publications

(3 citation statements)

References 26 publications

(32 reference statements)

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“…Moreover, the memory cell must be power efficient, area-efficient, and robust to any process variation. The stability of the cell can be analyzed with the help of a butterfly curve [26,27]. SRAM Stability can be calculated by SNM which is defined as the maximum noise voltage that the cell node can withstand without altering its value during any operation.…”

Section: Sram Cellmentioning

confidence: 99%

A 4 × 4 8T-SRAM array with single-ended read and differential write scheme for low voltage applications

Duari

Birla

Singh

2021

Semicond. Sci. Technol.

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In ultra-low-power applications, the design of power-efficient static random access memory (SRAM) is a major concern as it plays a significant part in leakage due to its higher density. In this paper, we have designed a power-efficient SRAM array that efficiently utilizes our SRAM cell for low-power and reliable memory applications. The proposed SRAM array is designed with an optimized 8T SRAM cell with minimum leakage and improved stability. The cell designed with 22 nm CMOS technology uses a stacking effect to further enhance leakage reduction and transmission gate as an access transistor to obtain better stability. Peripheral circuitry like address decoder, write driver, pre-charge, and sense amplifier are designed with optimum transistor sizing to get superior results in terms of area occupied and power consumption. The read and write access time for the cell is found to be 12 ps and 10 ps respectively. In line with the 22 nm technology node, the power is calculated for the array as 0.42 µW.

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Section: Sram Cellmentioning

confidence: 99%

A 4 × 4 8T-SRAM array with single-ended read and differential write scheme for low voltage applications

Duari

Birla

Singh

2021

Semicond. Sci. Technol.

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“…Feedback mechanism using Schmitt trigger-based SRAMs are proposed in [15], [16]. Dual port SRAM for imptoved stability has been proposed in [17]. FinFET SRAM with minimum variatins and improved stability has been proposed in [18].…”

Section: Literature Reviewmentioning

confidence: 99%

A 9T FinFET SRAM cell for ultra-low power application in the subthreshold regime

et al. 2021

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Due to the scaling of the CMOS, the limitations of these devices raised the need for alternative nano-devices. Various devices are proposed like FinFET, TFET, CNTFET. Among these, the FinFET emerges as one of the promising devices which can replace the CMOS due to its low leakage in the nanometer regime. The electronics devices are nowadays more compact and efficient in terms of battery consumption. The CMOS SRAMs have been replaced by the FinFET SRAMs due to the scaling limitations of the CMOS. Two FinFET SRAM cells have been which power efficient are and having high stability. Performance comparison of these cells has been done to analyze the leakage power and the static noise margins. The simulation of the cells is done at 20 nm FinFET technology. It has been analyzed that the write margin of improved 9T SRAM cell achieves an improvement of 1.49x. The read margin is also showing a drastic improvement over the existing cells which has been compared in the paper. The hold margin was found to be better in the case of the proposed SRAM cell at 0.4 V. The gate length has been varied to find the effect on read margin with gate length.

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“…IG operation starts when two gates have dissimilar voltages and the remaining gate is employed to switch devices and control transistor threshold voltage [6][7][8]. Te various height elements of a fn are quantized width (W) and H fn [9,10]. Te quantization width of a SG FinFET and quantization width of IG FinFET can be calculated using the following equation:…”

Section: Introductionmentioning

confidence: 99%

Design and Development of Efficient SRAM Cell Based on FinFET for Low Power Memory Applications

Rao¹,

Mamidipaka²,

Raghutu³

et al. 2023

Journal of Electrical and Computer Engineering

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Stationary random-access memory (SRAM) undergoes an expansion stage, to repel advanced process variation and support ultra-low power operation. Memories occupy more than 80% of the surface in today’s microdevices, and this trend is expected to continue. Metal oxide semiconductor field effect transistor (MOSFET) face a set of difficulties, that results in higher leakage current (Ileakage) at lower strategy collisions. Fin field effect transistor (FinFET) is a highly effective substitute to complementary metal oxide semiconductor (CMOS) under the 45 nm variant due to advanced stability. Memory cells are significant in the large-scale computation system. SRAM is the most commonly used memory type; SRAMs are thought to utilize more than 60% of the chip area. The proposed SRAM cell is developed with FinFETs at 16 nm knot. Power, delay, power delay product (PDP), Ileakage, and stationary noise margin (SNM) are compared with traditional 6T SRAM cells. The designed cell decreases leakage power, current, and read access time. While comparing 6T SRAM and earlier low power SRAM cells, FinFET-based 10T SRAM provides significant SNM with reduced access time. The proposed 10T SRAM based on FinFET provides an 80.80% PDP reduction in write mode and a 50.65% PDP reduction in read mode compared to MOSEFET models. There is an improvement of 22.20% in terms of SNM and 25.53% in terms of Ileakage.

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Dual Port 8T SRAM Cell Using FinFET & CMOS Logic for Leakage Reduction and Enhanced Read & Write Stability

Cited by 10 publications

References 26 publications

A 4 × 4 8T-SRAM array with single-ended read and differential write scheme for low voltage applications

A 4 × 4 8T-SRAM array with single-ended read and differential write scheme for low voltage applications

A 9T FinFET SRAM cell for ultra-low power application in the subthreshold regime

Design and Development of Efficient SRAM Cell Based on FinFET for Low Power Memory Applications

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