Static Random-Access Memory cells with ultralow leakage and superior stability are the primary choice of embedded memories in contemporary smart devices. This paper presents a novel 8T SRAM cell with reduced leakage and improved stability. The proposed SRAM cell uses a stacking effect to reduce leakage and transmission gate as an access transistor to enhance stability. The performance of the proposed 8T SRAM cell with a stacked transistor has been analyzed based on the power consumption and static noise margin (RSNM, HSNM, and WSNM). The power consumption in the case of FinFET based 8T cell is found to be 572 pW at 22 nm technology node, which is reduced by a factor nearly as compared to that of CMOS based 8T cell. Further, in the case of FinFET based novel 8T SRAM cell at 22 nm technology node, the power consumption is found to be reduced by a factor of as compared to that of FinFET based conventional 6T SRAM cell. WSNM, HSNM, and RSNM of the 8T SRAM cell designed with FinFET logic are observed as 240 mV, 370 mV, and 120 mV respectively at 0.9 V supply voltage. When comparing with conventional 6T FinFET Cell, the proposed Cell shows 20%, 5.11%, and 7% improvement in WSNM, HSNM, and RSNM, respectively. The sensitivity of SNM with temperature variation is also analyzed and reported. Further, the results obtained confirm the robustness of the proposed SRAM cells as compared to several recent works.
In ultra-low-power applications, the design of power-efficient static random access memory (SRAM) is a major concern as it plays a significant part in leakage due to its higher density. In this paper, we have designed a power-efficient SRAM array that efficiently utilizes our SRAM cell for low-power and reliable memory applications. The proposed SRAM array is designed with an optimized 8T SRAM cell with minimum leakage and improved stability. The cell designed with 22 nm CMOS technology uses a stacking effect to further enhance leakage reduction and transmission gate as an access transistor to obtain better stability. Peripheral circuitry like address decoder, write driver, pre-charge, and sense amplifier are designed with optimum transistor sizing to get superior results in terms of area occupied and power consumption. The read and write access time for the cell is found to be 12 ps and 10 ps respectively. In line with the 22 nm technology node, the power is calculated for the array as 0.42 µW.
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