Soft self-synchronising codes for self-calibrating communication

Ienne

IEEE Des. Test. Comput.

et al. 2004

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RECENT SILICON TECHNOLOGIES used for SoCs are increasingly different from original CMOS, which was an almost ideal digital technology. Second-order effects of different sorts, such as capacitive or inductive crosstalk, have become more critical because of a wealth of physical phenomena, including 3D and quantum effects. Similarly, ever-decreasing geometries are widening the spread of electrical parameters linked to imprecision in the manufacturing process. All these factors contribute significantly to design process complexity. Without a dramatic, unforeseen change in circuit and manufacturing technology, this situation can only get worse.The adopted design methodologies have always been based on worst-case design approaches. Gate and interconnect delays are a typical example. Circuits clock registers only when data is sure to be stable, and designers use worst-case analysis-as determined, for example, by static timing analyzers-to achieve this timing estimate. Designers simply model all sources of deviation from the nominal situation and total them to determine the most conservative estimate of the incurred delay.Observed trends in worst-case analysis for current design methodologies could invalidate the benefits of faster, scaled-down semiconductor technologies. As a result, large capital investments in deep-submicron silicon fabrication might not return competitive chips. Worst-case design will show diminishing returns in speed as designers scale down devices and supply voltages. The complex interaction of several physical factors will become increasingly harder to model accurately, pushing designers toward ever more conservative assumptions. Although some research aims to improve the accuracy of worst-case static timing estimations, 1 a more radical approach is needed. Otherwise, there will be a heavy price to pay-mostly in terms of energy consumption-even as power savings becomes a primary goal in many SoC applications. Figure 1 illustrates the point with a simple qualitative example. Recall that accurate knowledge of the delay and voltage relation is key for many optimization techniques, such as transistor sizing and dynamic voltage scaling. The nominal relation between delay and supply voltage is modified by several physical phenomena, whose cumulative effects constitute a worst-case relation. Therefore, at a given supply voltage, V DD , a designer will assume the most conservative delay-that is, that the operating point is not, for instance, A but B-and implement the design accordingly. However, at a particular instant, the device is likely to be operating under far more favorable conditions-for instance, with a lower delay indicated by operating point C. This implies a waste of energy because operation at reduced voltage V DD ′ (B′) On-Chip Self-Calibrating Communication Techniques Robust to Electrical Parameter VariationsEditor's note: Dynamic self-calibration holds the promise of overcoming conservative worstcase design techniques needed to combat deep-submicron process and operating variations. This ...

Section: Delay-insensitive Encodingmentioning

confidence: 99%

On-chip self-calibrating communication techniques robust to electrical parameter variations

Ienne

IEEE Des. Test. Comput.

et al. 2004

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“…We have bounded and approximated the residual word error rate of linear error detecting codes (under some assumptions about the code) over the timing error channel [11]. We have also upper bounded and approximated the residual word error rate of alternating-phase encoding using linear codes.…”

Section: Alternating-phase Encodingmentioning

confidence: 99%

“…Alternating-phase encoding has been proposed and studied as a low wiring overhead scheme offering a strong robustness to both timing and additive errors [11]. We describe it briefly.…”

Section: Alternating-phase Encodingmentioning

confidence: 99%

Designing Robust Checkers in the Presence of Massive Timing Errors

12th IEEE International on-Line Testing Symposium (IOLTS'06)

Ienne

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So far, performance and reliability of circuits have been determined by worst-case characterization of silicon and environmental noise. As new deep sub-micron technologies exacerbate process variations and reduce noise margins, worstcase design will eventually fail to meet an aggressive combination of objectives in performance, reliability, and power. In order to circumvent these difficulties, researchers have recently proposed a new design paradigm: self-calibrating circuits. Design parameters (e.g., operating points) of selfcalibrating circuits are set by monitoring correctness of their operation, thus enabling to dynamically trade reliability for power or performance, depending on actual silicon capabilities and noise conditions.In this paper, we study the problem of detecting errors caused by self-calibration of the supply voltage and frequency of an on-chip link. These errors are caused by operation at sub-critical voltage and may be numerous. We attack the problem with a coding technique. We also discuss an alternative approach using double sampling flip-flops. We stress the complementarity of the two approaches and show how they can be combined. Finally, we consider extending our work to computation. We give preliminary research directions on the detection of errors induced by self-calibration for an adder.

“…Because, a priori, any bit error rate can be encountered, the residual word error rate guaranteed by the CRC-8 alternating-phase code is roughly of 10 −2 (i.e., the maximum value of the curve). This maximum can be decreased by exploiting a latency-reliability tradeoff [8]. Furthermore, we expect the middle range of bit error rate to correspond to a very tiny voltage range (for a fixed frequency), which results in the link controller to remain mostly in the first biterror rate range and, sometimes, explore the third range.…”

Section: Self-calibrating Communicationmentioning

confidence: 99%

“…Due to this fact, classic error detecting codes cannot be used in selfcalibrating links. Alternating-phase codes are a simple extension of classic error detecting codes that incorporate temporal information about the data sequence within the redundant bits [8]. They detect all timing errors (i.e., ε res w = 0) when the raw bit error rate is 1.…”

Section: Self-calibrating Communicationmentioning

confidence: 99%

Self-Calibrating Networks-On-Chip

2005 IEEE International Symposium on Circuits and Systems

Micheli

et al.

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Abstract-Networks-on-chip provide an elegant framework to efficiently reuse predesigned cores. However, reuse of cores is jeopardized by new deep sub-micron noise effects that challenge reliability of CMOS technology. Moreover, noise margins are further reduced as supply voltage scale down. We advocate that self-calibrating techniques will be needed to maintain acceptable design trade-off between energy, performance, and reliability. As a result, self-calibrating techniques have to be integrated within networks-on-chip. This paper presents a selfcalibrating link and discusses qualitatively the problem of controlling adaptively its voltage and frequency.