On-chip self-calibrating communication techniques robust to electrical parameter variations

Abstract

RECENT SILICON TECHNOLOGIES used for SoCs are increasingly different from original CMOS, which was an almost ideal digital technology. Second-order effects of different sorts, such as capacitive or inductive crosstalk, have become more critical because of a wealth of physical phenomena, including 3D and quantum effects. Similarly, ever-decreasing geometries are widening the spread of electrical parameters linked to imprecision in the manufacturing process. All these factors contribute significantly to design process complexity. Without a dramatic, unforeseen change in circuit and manufacturing technology, this situation can only get worse.The adopted design methodologies have always been based on worst-case design approaches. Gate and interconnect delays are a typical example. Circuits clock registers only when data is sure to be stable, and designers use worst-case analysis-as determined, for example, by static timing analyzers-to achieve this timing estimate. Designers simply model all sources of deviation from the nominal situation and total them to determine the most conservative estimate of the incurred delay.Observed trends in worst-case analysis for current design methodologies could invalidate the benefits of faster, scaled-down semiconductor technologies. As a result, large capital investments in deep-submicron silicon fabrication might not return competitive chips. Worst-case design will show diminishing returns in speed as designers scale down devices and supply voltages. The complex interaction of several physical factors will become increasingly harder to model accurately, pushing designers toward ever more conservative assumptions. Although some research aims to improve the accuracy of worst-case static timing estimations, 1 a more radical approach is needed. Otherwise, there will be a heavy price to pay-mostly in terms of energy consumption-even as power savings becomes a primary goal in many SoC applications. Figure 1 illustrates the point with a simple qualitative example. Recall that accurate knowledge of the delay and voltage relation is key for many optimization techniques, such as transistor sizing and dynamic voltage scaling. The nominal relation between delay and supply voltage is modified by several physical phenomena, whose cumulative effects constitute a worst-case relation. Therefore, at a given supply voltage, V DD , a designer will assume the most conservative delay-that is, that the operating point is not, for instance, A but B-and implement the design accordingly. However, at a particular instant, the device is likely to be operating under far more favorable conditions-for instance, with a lower delay indicated by operating point C. This implies a waste of energy because operation at reduced voltage V DD ′ (B′) On-Chip Self-Calibrating Communication Techniques Robust to Electrical Parameter VariationsEditor's note: Dynamic self-calibration holds the promise of overcoming conservative worstcase design techniques needed to combat deep-submicron process and operating variations. This ...

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