Abstract-Systems-on-Chip (SoC) design involves several challenges, stemming from the extreme miniaturization of the physical features and from the large number of devices and wires on a chip. Since most SoCs are used within embedded systems, specific concerns are increasingly related to correct, reliable, and robust operation. We believe that in the future most SoCs will be assembled by using large-scale macro-cells and interconnected by means of on-chip networks. In this paper, we examine some physical properties of on-chip interconnect busses, with the goal of achieving fast, reliable, and low-energy communication. These objectives are reached by dynamically scaling down the voltage swing, while ensuring data integrity-in spite of the decreased signal to noise ratio-by means of encoding and retransmission schemes. In particular, we describe a closed-loop voltage swing controller that samples the error retransmission rate to determine the operational voltage swing. We present a control policy which achieves our goals with minimal complexity; such simplicity is demonstrated by implementing the policy in a synthesizable controller. Such a controller is an embodiment of a self-calibrating circuit that compensates for significant manufacturing parameter deviations and environmental variations. Experimental results show that energy savings amount up to 42%, while at the same time meeting performance requirements.Index Terms-Electrical parameter variations, interconnect for networks-on-chip, low-power systems-on-chip (SoC), self-calibrating designs, VLSI design methodology.

Systems-on-Chip (SoC) are evolving toward complex heterogeneous multiprocessors made of many predesigned macrocells or subsystems with application-specific interconnections. Intra-chip interconnects are thus becoming one of the central elements of SoC design and pose conflicting goals in terms of low energy per transmitted bit, guaranteed signal integrity, and ease of design. This work introduces and shows first results on a novel interconnect system which uses low-swing signalling, error detection codes, and a retransmission scheme; it minimises the interconnect voltage swing and frequency subject to workload requirements and S/N conditions. Simulation results show that tangible savings in energy can be attained while achieving at the same time more robustness to large variations in actual workload, noise, and technology quality (all quantities easily mispredicted in very complex systems and advanced technologies). It can be argued that traditional worst-case correct-by-design paradigm will be less and less applicable in future multibillion transistor SoC and deep sub-micron technologies; this work represents a first example towards robust adaptive designs.

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INTRODUCTIONSelf-calibrating designs rely on two key hypothesis, namely the possibility to (i) detect that the system is not operating correctly, and (ii) improve the system reliability at some cost-e.g., energy. In this paper, we focus on the former issue, in the context of communication. As far as communication tasks are concerned, correct operation is assessed if it is possible to determine whether a sequence of data has been received correctly. The voltage and frequency of the link can then be varied to ensure reliability. In practice, we are looking for an encoding scheme that determines, independently of the speed at which the link is operated, (a) if the received data is correct and (b) if it is the next piece of data to be received in sequence. The encoding has to be speed-independent since no assumption is made on signal propagation time. As a motivational example illustrating a situation where such an encoding scheme is required, consider a communication link where the voltage and frequency are set adaptively by a self-calibrating controller [11], as depicted in Figure 1. The encoding scheme has to detect errors originated by overaggressive operation. The difficulty does not come from

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