A robust self-calibrating transmission scheme for on-chip networks

Abstract

Abstract-Systems-on-Chip (SoC) design involves several challenges, stemming from the extreme miniaturization of the physical features and from the large number of devices and wires on a chip. Since most SoCs are used within embedded systems, specific concerns are increasingly related to correct, reliable, and robust operation. We believe that in the future most SoCs will be assembled by using large-scale macro-cells and interconnected by means of on-chip networks. In this paper, we examine some physical properties of on-chip interconnect busses, with the goal of achieving fast, reliable, and low-energy communication. These objectives are reached by dynamically scaling down the voltage swing, while ensuring data integrity-in spite of the decreased signal to noise ratio-by means of encoding and retransmission schemes. In particular, we describe a closed-loop voltage swing controller that samples the error retransmission rate to determine the operational voltage swing. We present a control policy which achieves our goals with minimal complexity; such simplicity is demonstrated by implementing the policy in a synthesizable controller. Such a controller is an embodiment of a self-calibrating circuit that compensates for significant manufacturing parameter deviations and environmental variations. Experimental results show that energy savings amount up to 42%, while at the same time meeting performance requirements.Index Terms-Electrical parameter variations, interconnect for networks-on-chip, low-power systems-on-chip (SoC), self-calibrating designs, VLSI design methodology.

A Survey Addressing On-Chip Interconnect: Energy and Reliability Considerations

“…The deterministic nature of ISI allows a variety of techniques to be used to suppress its effect. In addition to FFE, DFE and ISI reduction encoding, which were introduced previously, [32] uses line multiplexing to temporally space the use of wires and thus reduce the impact of ISI on their signals, while [33] proposes using error-rate controlled DVFS in order to increase the delay and thus adaptively reduce the effect of ISI, when errors are detected.…”

Self-Calibrating Networks-On-Chip

“…The computation of an average delay is too complex for the limited resources available to an on-chip link controller [10]. As a result, we approximate the average delay by the delay experienced by the last word queued in the FIFO.…”

“…The latter issue is not critical in the sense that naive thresholdbased algorithms grant significant energy saving, while not compromizing reliability [10]. Such an algorithm is depicted in Fig.…”

“…In addition, the design of a self-calibrating on-chip link has been thoroughly studied [10]. In particular, the power overhead incurred has been estimated.…”

On-chip data communication : analysis, optimization and circuit design

“…When a dedicated supply voltage is available to generate the low-swing signal, then the power is again quadratically dependent on the swing. Many low-swing techniques with a dedicated supply voltage (either generated on-or off-chip) for the transmitter have therefore been introduced in the past [15,84,85,182].…”