2012
DOI: 10.5402/2012/916259
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A Survey Addressing On-Chip Interconnect: Energy and Reliability Considerations

Abstract: Scaling CMOS process technology continues to enable increased levels of system integration, leading to on-chip communication demands beyond what traditional digital signaling techniques can efficiently provide with sufficient reliability. In this paper we survey the state of the art of on-chip interconnect techniques for improving performance, energy, and reliability and provide a review of interconnect reliability considerations. Finally, we provide a case study to evaluate the efficiency of error correcting … Show more

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Cited by 12 publications
(5 citation statements)
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“…As mentioned above, the WNoC scenario has very challenging end-to-end latency requirements in the range of subµs [98] with high reliability (typical Bit-Error-Ratios (BERs) lower than 10 −15 [98], [110] to compete with that of onchip wires). As the chips are generally shielded, security issues related to on-chip communication are not of paramount importance.…”
Section: On-chip Communicationmentioning
confidence: 99%
“…As mentioned above, the WNoC scenario has very challenging end-to-end latency requirements in the range of subµs [98] with high reliability (typical Bit-Error-Ratios (BERs) lower than 10 −15 [98], [110] to compete with that of onchip wires). As the chips are generally shielded, security issues related to on-chip communication are not of paramount importance.…”
Section: On-chip Communicationmentioning
confidence: 99%
“…On the other hand, the ACDMA crossbars adopt parallel binary signaling to carry the crossbar sum instead of multilevel or analog signaling which enhances their robustness. According to [14], while full-swing digital implementations have typically been able to assume BER values less than 10 −15 over the operating range of voltages and frequencies, this assumption does not hold true for custom low-swing interconnects and modern deep sub-micron circuits.…”
Section: Acdma Communication Reliabilitymentioning
confidence: 99%
“…As mentioned above, the WNoC scenario has very challenging end-to-end latency requirements in the range of subµs [49] with high reliability (typical Bit-Error-Ratios (BERs) lower than 10 −15 [49], [56] to compete with that of onchip wires). As the chips are generally shielded, security issues related to on-chip communication are not of paramount importance.…”
Section: On-chip Communicationmentioning
confidence: 99%