Soft Errors Induced by High-Energy Electrons

Gadlage, Matthew J.; Roach, A.; Duncan, Adam R.; Williams, Aaron M.; Bossev, Dobrin P.; Kay, Matthew

doi:10.1109/tdmr.2016.2634626

Cited by 63 publications

(26 citation statements)

References 22 publications

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“…Also, it seems that the cross sections for larger events decrease with the multiplicity, but remain on the same order. There are hints as well of a higher cross section for events affecting an even number (4,6,8) of cells . This can be just a random statistical fluctuation due to the low number of observed events but a similar behavior has been found in other memories [23].…”

Section: Cross Sections For Different Eventsmentioning

confidence: 95%

Single Event Upsets Under 14-MeV Neutrons in a 28-nm SRAM-Based FPGA in Static Mode

Fabero

Mecha

Franco

et al. 2020

IEEE Trans. Nucl. Sci.

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A sensitivity characterization of a Xilinx Artix-7 FPGA against 14.2 MeV neutrons is presented. The content of the internal SRAMs and flip-flops were downloaded in a PC and compared with a golden version of it. Flipped cells were identified and classified as cells of the configuration RAM, BRAM, or flip-flops. SBUs and MCUs with multiplicities ranging from 2 to 8 were identified using a statistical method. Possible shapes of multiple events are also investigated, showing a trend to follow wordlines. Finally, MUSCA SEP3 was used to make assesment for actual environments and an improvement of SEU injection test is proposed.

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Section: Cross Sections For Different Eventsmentioning

confidence: 95%

Single Event Upsets Under 14-MeV Neutrons in a 28-nm SRAM-Based FPGA in Static Mode

Fabero

Mecha

Franco

et al. 2020

IEEE Trans. Nucl. Sci.

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“…N the nano-scale CMOS technology, the electron devices in circuits and systems are becoming more sensitive to soft errors due to the aggressive scaling down of the feature sizes of transistors. Soft errors are typically caused by the striking of particles like neutrons, protons and heavy ions in space, alpha particles in packaging, and high-energy electrons [1,2]. When an energetic particle hits the diffusion region of a reverse bias transistor of a storage module, the generated charge can be collected by the nearby junctions via drift and diffusion mechanisms, resulting in voltage transients referred as a single node upset (SNU).…”

Section: Introductionmentioning

confidence: 99%

Novel Low Cost, Double-and-Triple-Node-Upset-Tolerant Latch Designs for Nano-scale CMOS

Yan

Lai

Zhang

et al. 2021

IEEE Trans. Emerg. Topics Comput.

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This paper presents two novel low cost, double-and-triple-node-upset tolerant latch designs. First, a novel low cost and double-node-upset (DNU) completely tolerant (LCDNUT) latch design is proposed. The latch mainly comprises a storage module (SM) feeding back to a 3-input C-element. The SM mainly consists of eight input-split inverters. Since the inputs of the C-element cannot be simultaneously flipped, the latch tolerates any DNU in the SM. When a single node in the SM and the output node are affected, the latch can self-recover from the DNU. Second, to completely tolerate any triple-node-upset (TNU), by replacing the C-element in the LCDNUT latch with a two-level error-interceptive module constructed from triple C-elements, a novel low cost and TNU completely tolerant (LCTNUT) latch design is proposed. Simulation results demonstrate the robustness of the proposed latches. Furthermore, due to the use of a high-speed transmission path, the clock-gating technology and fewer transistors, the proposed LCTNUT latch reduces the delay-power-area product by approximately 99.39% and has a low sensitivity to the process-voltage-and-temperature variation effects, compared with currently the only TNU completely tolerant latch design.

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“…As a result, the values of circuit nodes can be easily disturbed by radiation effects. The striking of radiative high-energy particles, such as neutrons, alpha particles, protons, heavy ions, electrons, and muons as well as the irradiation of high-energy X-ray and laser, etc., can easily cause soft errors to modern advanced CMOS circuits [1][2]. Soft errors can cause potential data corruptions, execution errors, and even system crashes.…”

Section: Introductionmentioning

confidence: 99%

Dual-Interlocked-Storage-Cell-Based Double-Node-Upset Self-Recoverable Flip-Flop Design for Safety-Critical Applications

Yan

Cui

et al. 2020

2020 IEEE International Symposium on Circuits and Systems (ISCAS)

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This paper presents a novel dual-interlocked storagecell (DICE)-based double-node-upset (DNU) self-recoverable, namely DURI-FF, in the nano-scale CMOS technology. The master latch of the DURI-FF cell consists of three transmission gates (TGs) and three interlocked DICEs with three common nodes. The common nodes are connected to TGs for value initialization. The slave latch of the DURI-FF cell comprises six TGs, six inverters and three interlocked DICEs. The outputs of the inverters respectively feed the internal nodes of the slave latch. The interlocked DICEs make the master latch and the slave latch DNU self-recoverable. Simulation results validate the DNU self-recoverability of the proposed DURI-FF cell. Moreover, compared with the state-of-the-art hardened flip-flop cells, the proposed DURI-FF cell achieves roughly 43% delay reduction at the cost of moderate silicon area and power dissipation.

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Soft Errors Induced by High-Energy Electrons

Cited by 63 publications

References 22 publications

Single Event Upsets Under 14-MeV Neutrons in a 28-nm SRAM-Based FPGA in Static Mode

Single Event Upsets Under 14-MeV Neutrons in a 28-nm SRAM-Based FPGA in Static Mode

Novel Low Cost, Double-and-Triple-Node-Upset-Tolerant Latch Designs for Nano-scale CMOS

Dual-Interlocked-Storage-Cell-Based Double-Node-Upset Self-Recoverable Flip-Flop Design for Safety-Critical Applications

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