Novel Low Cost, Double-and-Triple-Node-Upset-Tolerant Latch Designs for Nano-scale CMOS

Abstract

This paper presents two novel low cost, double-and-triple-node-upset tolerant latch designs. First, a novel low cost and double-node-upset (DNU) completely tolerant (LCDNUT) latch design is proposed. The latch mainly comprises a storage module (SM) feeding back to a 3-input C-element. The SM mainly consists of eight input-split inverters. Since the inputs of the C-element cannot be simultaneously flipped, the latch tolerates any DNU in the SM. When a single node in the SM and the output node are affected, the latch can self-recover from the DNU. Second, to completely tolerate any triple-node-upset (TNU), by replacing the C-element in the LCDNUT latch with a two-level error-interceptive module constructed from triple C-elements, a novel low cost and TNU completely tolerant (LCTNUT) latch design is proposed. Simulation results demonstrate the robustness of the proposed latches. Furthermore, due to the use of a high-speed transmission path, the clock-gating technology and fewer transistors, the proposed LCTNUT latch reduces the delay-power-area product by approximately 99.39% and has a low sensitivity to the process-voltage-and-temperature variation effects, compared with currently the only TNU completely tolerant latch design.

Design of a Highly Reliable SRAM Cell with Advanced Self-Recoverability from Soft Errors

“…To make a fair comparison with the state-of-the-art typical SRAM cells, such as the 6T, ST10T [4], NASA13T [6], NS10T [7], RHD12T [8], RSP14T [9], RH12T [10] and DNUSRM [11], the same simulation conditions described in the above section were used for SRAM implementations. Table I shows the reliability and overhead comparison results among the unhardened/hardened SRAMs in terms of SNU recoverability, DNU recoverability, write access time (WAT), read access time (RAT), average power dissipation (dynamic and static), and silicon area which is measured with the method in [22].…”

“…Moreover, it is reported in [22] that process, voltage and temperature (PVT) variations have increasing impacts on storage cells. It is reported in [9] that static noise margin (SNM)…”

Design of a Sextuple Cross-Coupled SRAM Cell with Optimized Access Operations for Highly Reliable Terrestrial Applications

“…To quantify various overhead of the proposed SCCS cell to make a fair comparison with the state-of-the-art typical SRAM cells described in Section I, the same simulation conditions described in the above section were used for all simulations. Table I shows the reliability and overhead comparison results among the unhardened/hardened SRAM cells in terms of SNU/DNU hardness, write access time (WAT), read access time (RAT), average power dissipation (dynamic and static), and silicon area measured with the method in [27].…”

Novel MTJ-Based Sensing Inverter Variation Tolerant Nonvolatile Flip-Flop in the Near-Threshold Voltage Region

“…In addition, scaling VDD and the technology nodes induces large process variations [34]- [35], soft errors [36], and manufacturing defects [37] that affect the sensing operation. In this regard, offset cancellation [14]- [15], upset tolerant [38]- [39], and defect tolerant [13] techniques are required to satisfy the stable sensing operation. Among these techniques, this paper focuses on the offset cancellation technique for process variation tolerance.…”