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Nonvolatile flip-flop (NV-FF) based systems can be effectively implemented in battery-limited internet of things (IoT) applications due to their zero standby power consumption and instant ON/OFF characteristics. Among various NV-FFs, spin-transfer-torque magnetic tunnel junction based NV-FFs are the most applicable due to their nonvolatility, high endurance, complementary metal-oxide-semiconductor (CMOS) compatibility, scalability, and rapid sensing and write speed due to its low resistance. However, they are subject to a degraded sensing margin for restoring operation with technology shrinks because of the increased process variation and reduced supply voltage. This paper proposes a novel NV-FF with a significantly superior offset-tolerance and reduction in read current (Iread) that produces read disturbance in comparison to state-of-the-art NV-FFs. Monte Carlo HSPICE simulation results based on industrycompatible 65-nm model parameters revealed that the proposed NV-FF can achieve a three-order improvement in the restore yield and a two-order reduction in the Iread when compared with state-of-the-art NV-FFs.

In recent years, the low power design of Internet of Things devices has become increasingly important. The most basic method to implement a low power design is to reduce static power consumption. In this regard, a spin-transfer-torque magnetic-tunnel-junction-based nonvolatile flip-flop (NVFF) is a promising candidate for storing the computing data while the power is off. However, as the technology node scales down, the process variation increases, leading to a restoration failure in previous NVFFs, especially in the near-threshold voltage (NTV) region. For better energy efficiency when operating the NVFF in the NTV region, this paper presents a novel NVFF that guarantees a target restore yield of 4σ and a target read disturbance margin of 6σ in the NTV region (0.6 V supply voltage), along with auto-zeroing and dynamic reference voltage (DRV) techniques, using only a single capacitor to improve the NVFF's restore yield. The Monte Carlo HSPICE simulation results using industry-compatible 28-nm model parameters show that the proposed NVFF satisfies both the target restore yield and the read disturbance margin, saving 44% restoration time compared with the current state-of-the-art NVFF, which does not satisfy the target restore yield despite having offset cancellation characteristic. INDEX TERMS Auto-zeroing, double sensing margin, dynamic reference voltage (DRV), magnetic tunnel junction (MTJ), near-threshold voltage (NTV), nonvolatile flip-flop (NVFF), sensing inverter variation tolerant (SIVT), sensing margin (SM).

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