Single Event Upsets Under 14-MeV Neutrons in a 28-nm SRAM-Based FPGA in Static Mode

Abstract

A sensitivity characterization of a Xilinx Artix-7 FPGA against 14.2 MeV neutrons is presented. The content of the internal SRAMs and flip-flops were downloaded in a PC and compared with a golden version of it. Flipped cells were identified and classified as cells of the configuration RAM, BRAM, or flip-flops. SBUs and MCUs with multiplicities ranging from 2 to 8 were identified using a statistical method. Possible shapes of multiple events are also investigated, showing a trend to follow wordlines. Finally, MUSCA SEP3 was used to make assesment for actual environments and an improvement of SEU injection test is proposed.

SEE sensitivity of a COTS 28-nm SRAM-based FPGA under thermal neutrons and different incident angles

“…The study has revealed angular dependencies with the occurrence of SBUs and MCUs that were extracted from the experimental results. These dependencies are consistent for all types of events (MCUs and MBUs), but they differ from the trends that were observed in a previous work where the same device was exposed to 14.2-MeV neutrons [10]. Thus, in general, thermal neutrons provoke events more easily than 14.2-MeV ones, but the angular effects of these particles differ mainly due to the fact that thermal neutrons do not provoke as many multiple events as fast ones at grazing angles.…”

“…The isotopic abundance of natural boron is 20% 10 B and 80% 11 B. The risk of introducing 10 B is the high cross-section for 10 B thermal neutron capture and subsequent production of energetic charged particles that can cause SEEs. The 10 B cross-section for thermal neutrons is dominated by the (n,α) reaction inducing emission of an alpha particle and a Lithium-ion with energies of 1.47 MeV and 0.84 MeV, respectively.…”

“…The experiments show that the temperature variation induced by a higher operating frequency impacts the CRAM cross-section. In [10], Fabero et al researched the response of a 28-nm SRAM-based Artix-7 FPGA against 14.2-MeV neutrons and analyzed the observed events using a statistical method. Researchers in [11] examined a Kintex-7 FPGA in the ATLAS Liquid Argon (LAr) Calorimeter at CERN against a broad spectrum of neutrons, protons, heavy-ions, and high-energy hadrons.…”

Area-Efficient Differential Fault Tolerance Encoding for Finite State Machines

“…The stuck-at-zero and stuck-at-one models are used, which represent the situation in which an energetic particle causes the fixed state of the storage temporally [26]. For the number of faults, [8] indicates that SEU is the most frequent fault, and single event multiple upset (SEMU) with up to three bits is dominant in modern integrated circuits [27]. To compute the fault rate of an FSM, it is operated for 1024 clock cycles and random faults using either stuck-at-zero or stuck-at-one models are inserted for one clock cycle [25,28].…”

“…Figure 8 shows the failure rate of the proposed method, in which a failure in FSM counts when either the output or the current state of normal operation without faults is different from that of a faulty operation. To account for the cases of both SEU and SEMU, various failure rates are computed under single, double, and triple fault injections [27], as depicted. Figure 8 shows that the failure ratio improves due the increase in the coverage and the Hamming distance caused by providing strong fault tolerance on more states.…”