Area-Efficient Differential Fault Tolerance Encoding for Finite State Machines

Park, Jiwoon; Yoo, Hyung-Joun

doi:10.3390/electronics9071110

Cited by 6 publications

(6 citation statements)

References 27 publications

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“…To diminish the number of literals, various methods of state assignment are used [45][46][47][48][49][50]. These methods can be found in many academic and industrial CAD tools.…”

Section: Related Workmentioning

confidence: 99%

Using Codes of Output Collections for Hardware Reduction in Circuits of LUT-Based Finite State Machines

et al. 2022

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A method is proposed which aims to reduce the hardware in FPGA-based circuits of Mealy finite state machines (FSMs). The proposed method is a type of structural decomposition method. Its main goal is the reducing the number of look-up table (LUT) elements in FSM circuits compared to the three-block FSM circuit. The main idea of the proposed method is the using codes of collections of FSM outputs for replacing the FSM inputs and state variables. The interstate transitions are defined using collections of outputs generated in two adjacent cycles of synchronization. One, of output collection codes, is kept into a register. To optimize block-generating FSM outputs, a new type of state codes is proposed. A state is encoded as an element of some class of states. This approach allows both the number of logic levels and inter-level interconnections in LUT-based FSM circuit to be diminished. An example of an LUT-based Mealy FSM circuit with the proposed method applied is shown. Moreover, the results of our research are represented. The research was conducted using the CAD tool Vivado by Xilinx. The experiments prove that the proposed approach allows the reduction of hardware compared with such known methods as Auto and One-hot of Vivado, and JEDI. Moreover, the proposed approach gives better results than a method based on the simultaneous replacement of inputs and encoding collections of outputs. Compared to circuits of the three-block FSMs, the LUT counts are reduced by an average of 10.07% without significant reduction in the value of operating frequency. The gain in LUT counts increases with the increasing the numbers of FSM states and inputs.

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“…To diminish the number of literals, various methods of state assignment are used [45][46][47][48][49][50]. These methods can be found in many academic and industrial CAD tools.…”

Section: Related Workmentioning

confidence: 99%

Using Codes of Output Collections for Hardware Reduction in Circuits of LUT-Based Finite State Machines

et al. 2022

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“…The problems of optimizing the characteristics of FSM circuits are discussed in many works, such as, for example, [30][31][32][33][34][35]. An analysis of these and many other works allowed us to draw the following conclusion.…”

Section: Related Workmentioning

confidence: 99%

“…This is SLUT8. Therefore, the circuit of CPF2 contains seven LUTs implementing SBFs (31) and (32). This means there are 14 LUTs on the first level of the logic circuit of FSM Ex2.…”

Section: Slut1mentioning

confidence: 99%

Reducing Hardware in LUT-Based Mealy FSMs with Encoded Collections of Outputs

2022

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A method is proposed that is focused on reducing the chip area occupied by logic elements creating the circuit of Mealy finite state machines (FSMs). The proposed method is aimed at FSM circuits implemented with internal resources of field-programmable gate arrays (FPGA). The required chip area is estimated by the number of look-up table (LUT) elements in a particular circuit. The method is based on mutual application of two methods of structural decomposition. The first of them is based on dividing the set of outputs and using unitary-maximum encoding of collections of FSM outputs. The second method is based on dividing the set of states by classes of compatible states. The optimization is achieved by replacing the maximum binary state codes by two-part codes proposed in this article. Each two-part state code consists of a code of a class including a particular state and a maximum binary code of this state inside a particular class. The proposed approach leads to three-level LUT-based Mealy FSM circuits. The first logic level generates three types of partial functions: unitary encoded outputs, variables encoding collections of outputs, and input memory functions. Each partial function is represented by a circuit including a single LUT. The LUTs from the second logic level generate final values of these functions. The LUTs from the third level implement outputs using collections of outputs. An example of synthesis applying the proposed method is discussed. The experiments were conducted using standard benchmark FSMs. Their results showed significant improving of the area occupied by an FSM circuit. The LUT count decreased on average by 9.49%. The positive side effect of the proposed method was increasing the value of the maximum operating frequency (on average, by 8.73%). The proposed method is advisable to use if a single-level LUT-based implementation of the FSM circuit is impossible.

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“…In our current paper, a method is proposed which aims at reducing the LUT count of three-block circuits of Mealy FSMs [15]. The values of N A(φ k ) can be reduced with the help of a proper state assignment [41][42][43]. The number of FSM state memory elements is in the range from R = log 2 M to R = M. The upper limit of this amount (R = M) corresponds to a one-hot state assignment.…”

Section: Related Workmentioning

confidence: 99%

Improving Hardware in LUT-Based Mealy FSMs

2022

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The main contribution of this paper is a novel design method reducing the number of look-up table (LUT) elements in the circuits of three-block Mealy finite-state machines (FSMs). The proposed method is based on using codes of collections of outputs (COs) for representing both FSM state variables and outputs. The interstate transitions are represented by output collections generated during two adjacent cycles of FSM operation. To avoid doubling the number of variables encoding of COs, two registers are used. The first register keeps a code of CO produced in the current cycle of operation; the code of a CO produced in the previous cycle is kept in the second register. There is given a synthesis example with applying the proposed method. The results of the research are shown. The research is conducted using the CAD tool Vivado by Xilinx. The experiments prove that the proposed approach allows reducing the hardware compared with such known methods as auto and one-hot of Vivado, and JEDI. Additionally, the proposed approach gives better results than a method based on the simultaneous replacement of inputs and encoding of COs. Compared to circuits of the three-block FSMs, the LUT counts are reduced by an average of 7.21% without significant reduction in the performance. Our approach loses in terms of power consumption (on average 9.62%) and power–time products (on average 10.44%). The gain in LUT counts and area–time products increases with the increase in the numbers of FSM states and inputs.

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Area-Efficient Differential Fault Tolerance Encoding for Finite State Machines

Cited by 6 publications

References 27 publications

Using Codes of Output Collections for Hardware Reduction in Circuits of LUT-Based Finite State Machines

Using Codes of Output Collections for Hardware Reduction in Circuits of LUT-Based Finite State Machines

Reducing Hardware in LUT-Based Mealy FSMs with Encoded Collections of Outputs

Improving Hardware in LUT-Based Mealy FSMs

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