Silicon-Germanium Strained Layer Materials in Microelectronics

Paul, Douglas J.

doi:10.1002/(sici)1521-4095(199903)11:3<191::aid-adma191>3.0.co;2-3

Cited by 140 publications

(82 citation statements)

References 75 publications

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“…1 The most widely used method of fabricating globally strained silicon for device processing employs SiGe virtual substrates as growth templates. In order to be acceptable for use in industry, strained layers must ideally be defect free and maintain strain during device processing.…”

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confidence: 99%

Misfit strain relaxation and dislocation formation in supercritical strained silicon on virtual substrates

Parsons

Parker

Leadley

et al. 2007

Applied Physics Letters

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Relaxation of strained silicon on 20% linear graded virtual substrates was quantified using high resolution x-ray diffraction and a defect etching technique. The thickness of strained silicon was varied between 10 and 180 nm. Relaxation was observed in layers below the critical thickness but increased to only 2% relaxation in the thickest layers even with annealings up to 950°C. Cross-sectional transmission electron microscopy revealed stacking faults present in layers thicker than 25 nm, and nucleated 90°Shockley partial dislocations forming microtwins in the thickest layer. These features are implicated in the impediment of the relaxation process.

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confidence: 99%

Misfit strain relaxation and dislocation formation in supercritical strained silicon on virtual substrates

Parsons

Parker

Leadley

et al. 2007

Applied Physics Letters

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“…strained SiGe, growth may either be on unstrained Si or a SiGe VS of lower alloy composition than the strained SiGe layer [6]. Modification to the electronic band structure and a reduced in-plane effective mass enhances hole mobility in compressively strained SiGe compared with unstrained Si.…”

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confidence: 99%

High-performance nMOSFETs using a novel strained Si/SiGe CMOS architecture

Olsen

O'Neill

Driscoll

et al. 2003

IEEE Trans. Electron Devices

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Abstract-Performance enhancements of up to 170% in drain current, maximum transconductance, and field-effect mobility are presented for nMOSFETs fabricated with strained-Si channels compared with identically processed bulk Si MOSFETs. A novel layer structure comprising Si/Si 0 7 Ge 0 3 on an Si 0 85 Ge 0 15 virtual substrate (VS) offers improved performance advantages and a strain-compensated structure. A high thermal budget process produces devices having excellent on/off-state drain-current characteristics, transconductance, and subthreshold characteristics. The virtual substrate does not require chemical-mechanical polishing and the same performance enhancement is achieved with and without a titanium salicide process.

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“…The conduction band discontinuities for quantum wells from theory 10 suggests values which are about 50% too large. 3 The present data does not yet allow an accurate estimate of the barrier heights to compare to theory. The decrease in the PVCR at temperatures below 40 K ͑Fig.…”

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confidence: 75%

“…The vast majority of the microelectronics industry, however, is based on Si and therefore there is great interest in attempting to create RTDs using Si/SiGe heterostructures. 3 The n-type system has the only room temperature demonstration of negative differential resistance ͑NDR͒ in Si-based RTDs with peak current densities up to 5 kA/cm 2 ͑Ref. 4͒ and peak-to-valley current ratios ͑PVCR͒ of up to 2.9 ͑Ref.…”

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confidence: 99%