Compressively strained Ge long channel ring-type pMOSFETs with high-κ Si/SiO 2 /HfO 2 /TiN gate stacks are fabricated on Si 0.2 Ge 0.8 virtual substrates. Effective oxide thickness is approximately 1.4 nm with low gate leakage current. A peak hole mobility of 640 cm 2 /V · s and up to a four times enhancement over the Si/SiO 2 universal curve are observed. Parasitic conduction within the Si-cap layers degrades the mobility at large vertical fields, although up to a 2.5 times enhancement over universal remains at a field of 0.9 MV/cm.
Relaxation of strained silicon on 20% linear graded virtual substrates was quantified using high resolution x-ray diffraction and a defect etching technique. The thickness of strained silicon was varied between 10 and 180 nm. Relaxation was observed in layers below the critical thickness but increased to only 2% relaxation in the thickest layers even with annealings up to 950°C. Cross-sectional transmission electron microscopy revealed stacking faults present in layers thicker than 25 nm, and nucleated 90°Shockley partial dislocations forming microtwins in the thickest layer. These features are implicated in the impediment of the relaxation process.
Strain relaxation has been studied in tensile strained silicon layers grown on Si 0.5 Ge 0.5 virtual substrates, for layers many times the critical thickness, using high resolution x-ray diffraction. Layers up to 30 nm thick were found to relax less than 2% by the glide of preexisting 60°d islocations. Relaxation is limited because many of these dislocations dissociate into extended stacking faults that impede the dislocation glide. For thicker layers, nucleated microtwins were observed, which significantly increased relaxation to 14%. All these tensile strained layers are found to be much more stable than layers with comparable compressive strain.
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