Shrunk-2-D: A Physical Design Methodology to Build Commercial-Quality Monolithic 3-D ICs

Panth, Shreepad; Samadi, Kambiz; Du, Yi; Lim, Sung Kyu

doi:10.1109/tcad.2017.2648839

Cited by 55 publications

(23 citation statements)

References 7 publications

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“…First, the design is partitioned into two tiers using a modified version of Shrunk-2D [17]. We start with a placed and routed 2D design that satisfies timing constraints.…”

Section: B Design Flowmentioning

confidence: 99%

“…This results in the overlap of standard cells. The standard cells are then partitioned into two tiers to remove the overlap by defining regular partitioning grids, and performing an area-balanced global min-cut [17]. We scale the placement coordinates instead of standard cell dimensions, as proposed in [17], since this method does not require modification to standard cell and technology LEF, which can be time-consuming and error-prone.…”

Section: B Design Flowmentioning

confidence: 99%

See 1 more Smart Citation

Reliable Power Delivery and Analysis of Power-Supply Noise During Testing in Monolithic 3D ICs

Koneru

Todri‐Sanial

Chakrabarty

2019

2019 IEEE 37th VLSI Test Symposium (VTS)

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Monolithic 3D (M3D) integration offers significant performance, power, and area benefits. However, the design of a reliable power-delivery network (PDN) is challenging for M3D ICs due to high power density and current demand per unit area. In addition, the higher susceptibility of interconnects to electromigration and stress migration increases the complexity of PDN design. We propose a framework to design a reliable PDN for M3D ICs using accurate electrical and reliability models. We leverage genetic programming to explore the design space to optimize the resources dedicated for power delivery in order to achieve reliable operation. We also analyze power-supply noise (PSN) during scan-based testing and compare it with that observed during functional operation. We quantify the impact of PSN during scan-based testing on yield loss. Our results show that the PDN design obtained using the proposed approach significantly increases the reliability of at least 40% of the wire segments in the PDN. In addition, the proposed PDN design reduces the worst-case power-supply droop by 52.5% compared to a baseline PDN. The yield loss due to power-supply droop for the proposed design is also significantly lower compared to a baseline PDN.

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“…First, the design is partitioned into two tiers using a modified version of Shrunk-2D [17]. We start with a placed and routed 2D design that satisfies timing constraints.…”

Section: B Design Flowmentioning

confidence: 99%

Section: B Design Flowmentioning

confidence: 99%

Reliable Power Delivery and Analysis of Power-Supply Noise During Testing in Monolithic 3D ICs

Koneru

Todri‐Sanial

Chakrabarty

2019

2019 IEEE 37th VLSI Test Symposium (VTS)

View full text Add to dashboard Cite

show abstract

“…This option has recently gained more attention [39], [40], [41], mainly thanks to advances of the processing technology [42]. The key feature of monolithic 3D ICs is that active layers are sequentially manufactured into one chip rather than bonded using separate dies.…”

Section: Monolithic 3d Icsmentioning

confidence: 99%

“…For placement, routing, and design closure of monolithic 3D ICs, the reuse of commercial 2D physical design tools has been demonstrated to lower the barrier for industry-wide acceptance [40], [47], [48], [49]. Nevertheless, due to its sequential processing nature, such 3D ICs cannot apply "plug-and-play" in- * 2 For example, the micro-bump bonding in TSV-based 3D ICs may be underfilled with BCB polymer layers.…”

Section: Monolithic 3d Icsmentioning

confidence: 99%

Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration

Knechtel

Sinanoglu

Elfadel

et al. 2017

IPSJ Transactions on System LSI Design Methodology

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Three-dimensional (3D) integration of electronic chips has been advocated by both industry and academia for many years. It is acknowledged as one of the most promising approaches to meet ever-increasing demands on performance, functionality, and power consumption. Furthermore, 3D integration has been shown to be most effective and efficient once large-scale integration is targeted for. However, a multitude of challenges has thus far obstructed the mainstream transition from "classical 2D chips" to such large-scale 3D chips. In this paper, we survey all popular 3D integration options available and advocate that using an interposer as system-level integration backbone would be the most practical for large-scale industrial applications and design reuse. We review major design (automation) challenges and related promising solutions for interposer-based 3D chips in particular, among the other 3D options. Thereby we outline (i) the need for a unified workflow, especially once full-custom design is considered, (ii) the current design-automation solutions and future prospects for both classical (digital) and advanced (heterogeneous) interposer stacks, (iii) the state-of-art and open challenges for testing of 3D chips, and (iv) the challenges of securing hardware in general and the prospects for large-scale and trustworthy 3D chips in particular.

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“…to their oorplanning methodology, they can achieve temperatures comparable or even smaller than the ones obtained with 2D technology [198], by using 2D oorplanning for creating 3D integrated designs using monolithic 3D [199]. Their process can achieve up to 12% and 8% power savings for a single block and SoC, respectively, when compared with their 2-D counterparts implemented using commercial tools.…”

Section: Future Workmentioning

confidence: 99%

Memory-Aware Scheduling for Fixed Priority Hard Real-Time Computing Systems

Chaparro-Baquero¹

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Shrunk-2-D: A Physical Design Methodology to Build Commercial-Quality Monolithic 3-D ICs

Cited by 55 publications

References 7 publications

Reliable Power Delivery and Analysis of Power-Supply Noise During Testing in Monolithic 3D ICs

Reliable Power Delivery and Analysis of Power-Supply Noise During Testing in Monolithic 3D ICs

Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration

Memory-Aware Scheduling for Fixed Priority Hard Real-Time Computing Systems

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