1989
DOI: 10.1109/33.49025
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Semiconductor interlevel shorts caused by hillock formation in Al-Cu metallization

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Cited by 27 publications
(6 citation statements)
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“…32 With these values, the thickness of the consumed Ti layer would be 59 nm at 450°C and 357 nm at 550°C after annealing for 30 min. [33][34][35] The formation of TiN is detected by x-ray diffraction after annealing at 700°C. The 80 nm-thick Ti layer is reacted about half way at 550°C (Fig.…”
Section: Discussionmentioning
confidence: 99%
“…32 With these values, the thickness of the consumed Ti layer would be 59 nm at 450°C and 357 nm at 550°C after annealing for 30 min. [33][34][35] The formation of TiN is detected by x-ray diffraction after annealing at 700°C. The 80 nm-thick Ti layer is reacted about half way at 550°C (Fig.…”
Section: Discussionmentioning
confidence: 99%
“…The enhanced formation of hillocks is attributed to the increase in substrate temperature with the application of radio frequency ͑rf͒ power. 15,16 To determine which factor controls hillock formation, the wafer temperature was measured in situ during plasma cleaning. Results indicate that the temperature range was 250-320°C during H 2 /N 2 plasma cleaning, as shown in Fig.…”
Section: Resultsmentioning
confidence: 99%
“…In figure 3 (d) a hillock between M1 and M2 layers is shown. These defects are generated by the thermal relaxation of the different layer materials [10,11]. In fact, due to the different coefficient of thermal expansion for Si and Al (the latter 10 times larger [11]), the thermal cycles that the sensor undergoes during production induce compressive stresses in the first Al layer.…”
Section: Pxd9 Quality Assurancementioning
confidence: 99%