Avoiding Cu Hillocks during the Plasma Process

Abstract

When Cu wafers are exposed to H 2 /N 2 plasma, hillocks are formed on the Cu wafer surface by a plasma cleaner with a surface wave plasma source. Plasma cleaning is divided into the initial stage and the rising temperature stage. Under a supply of H 2 /N 2 gas and with the plasma power turned on, the H radicals first restore native copper oxide to pure copper. The N radicals then compete with the H radicals, and diffuse to the Cu grain boundary, which is the initial stage. During the rising temperature stage, plasma energy is absorbed by the Cu surface, and the wafer temperature increases rapidly. Consequently, plasma-enhanced compressive stress leads to the formation of Cu hillocks. For a plasma with a higher N/H radical ratio, more N radicals diffusing to the Cu grain boundary results in more Cu-N compounds, which make up the main source of stress during H 2 /N 2 plasma cleaning. Experimental results indicate that using a plasma cleaner with an inductively coupled plasma source can achieve a lower N/H radical ratio, thus avoiding the formation of Cu hillocks.The Cu dual damascene process has been widely employed for fabricating multilevel interconnection schemes in ultralarge scale integration ͑ULSI͒ circuits. This is because Cu dual damascene wiring provides significant advantages over the conventional Al metallization process. Therefore, many issues related to this process have been studied in detail. 1-5 Some of these issues affect the yield of the via chain. 4-6 The first via approach for the dual damascene structure consists of the following sequence. ͑i͒ Via etching through the whole dielectric stack (trench ϩ via), and then bottom antireflective coating ͑BARC͒ via filling, (ii) trench lithography, (iii) BARC etch back, (iv) trench etching in fluorinated silicate glass ͑FSG͒, and then O 2 -based plasma cleaning, and (v) capping nitride removal, and then O 2 -based plasma cleaning. The schematic process is shown in Fig. 1. Sometimes, it is difficult to stop the etch on the thin nitride film during via etching due to low or unstable oxide/nitride selectivity. Therefore, the Cu underlayer will be exposed to air after via etching. Moreover, it is observed that using only wet solvent cleaning after nitride removal will result in some residue, as shown in Fig. 2. Therefore, it is also necessary to use plasma cleaning after nitride removal. For conventional postetch cleaning technology used in the Al interconnection process, most recipes use O 2 -based plasma with high temperatures of 250-275°C. Even though the Al underlayer is exposed to air after via or trench etching, it is notable that the thin Al 2 O 3 compound on Al surfaces is not oxidized continuously during O 2 -based plasma cleaning. However, the weak Cu oxide on the Cu surface cannot provide an effective barrier to prevent Cu bulk from continuous oxidization at high temperature. These copper oxides may possibly cause difficulty in subsequent cleaning and reduction in interconnection yield. Therefore developing a new dry cleaning technology for Cu dual...

Comparison of H2and NH3Treatments for Copper Interconnects

“…Hillocks are easily formed on a Cu surface in a thermalplasma environment and this formation must be minimized. A previous study [16] pointed out that the formation of Cu hillocks is related to the thermal budget. This study also demonstrates that the density of Cu hillocks increases with treatment time.…”

Copper Diffusion and Corrosion Behavior Through the Hillock Defect Found Beneath the Weak SiN Dielectric Barrier in Dual Damascene Process

“…However, when adopting copper as a interconnect metal, many issues related to this process have happened. For example, diffusion barrier must be used to strengthen diffusion inhibition as well as adhesion in the copper based metallization because copper diffuses fast through oxide and silicon [2][3]. And copper has higher coefficient of thermal expansion than other materials used in semiconductor.…”

Copper Hillock Induced Copper Diffusion and Corrosion Behavior in a Dual Damascene Process

“…For example, a diffusion barrier is required for copper diffusion inhibition in the metallization because of the high diffusivity of copper through oxide and silicon. 2,3 Also, copper has a high thermal expansion coefficient compared to other materials used in VLSI technology and such a characteristic results in thermal stress in a stack of copper and dielectric layers. The thermal expansion mismatch of copper and interlayer dielectric ͑ILD͒ layers was reported to cause hillock defects.…”

“…5,6 Other research has reported that plasma cleaning plays a dominant role in hillock formation. 2 Also, grain boundary migration was found to be critically involved in the electromigration induced hillocks. 7 Although there has been much research on the root cause of copper hillocks, there has been little research on how the hillock leads to interconnect failure.…”