As integrated circuit dimensions continue to decrease, RC delay, crosstalk noise and power dissipation of the interconnect structure become limiting factors for ultra-large-scale integration of integrated circuits. Materials with low dielectric constant are being developed to replace silicon dioxide as interlevel dielectrics. This chapter provides an overview on the basic issues of low-k dielectrics for interconnect applications and serves as a framework to introduce the topics covered in contributed chapters of this book. First, the general approach to reduce the dielectric constant is discussed, emphasizing the correlation of dielectric polarizability with bonding characteristics and the tradeoff of dielectric constant and mechanical properties. Then, the material properties and integration requirements are discussed, followed by a discussion on the development of characterization techniques. Finally, the development of porous low-k materials is briefly discussed and its challenge is highlighted by recent results obtained on the porosity effect on material properties of porous organosilicate films. IntroductionContinuing improvement in device density and performance has significantly impacted the feature size and complexity of the wiring structure for on-chip interconnects. As the minimum device dimensions reduce beyond 250 nm, the increase in propagation delay, crosstalk noise and power dissipation of the interconnect structure become limiting factors for ultra-large-scale integration (ULSI) of integrated circuits. The impact due to interconnect scaling on performance can be examined by evaluating the RC delay of multilevel interconnects. Figure 1.1 shows a schematic diagram of a typical element in multilevel interconnects, where P represents the line pitch, W the line width, S the line spacing, T the line thickness and the dielectric thickness above and below the interconnect is equal. The RC delay can be deduced using a simple first-order model and is given as [1]where ρ is the metal resistivity, ε 0 the vacuum permittivity, k the relative dielectric constant and L the line length. Accordingly, the RC delay is determined by two sets of parameters: first, material properties including the metal P.S. Ho et al. (eds.), Low Dielectric Constant Materials for IC Applications

The fracture characteristics of metal/polymer line structures formed by depositing Au/Cr lines on a semiflexible polyimide, pyromellitic dianhydride-oxydianiline (PMDA-ODA), substrate have been investigated using a stretch deformation technique. The delamination behavior, fracture morphology, fracture energy, and energy dissipation rate have been determined as a function of line width and thickness. The metal dimension was found to influence the crack formation mode and morphology. The experimental studies were supplemented by finite-element analysis to evaluate the stress distribution and deformation energetics of the line structure, which takes into account the plastic deformation of the metal and the polymer. Results from this analysis show that the observed fracture characteristics can be attributed to the edge and thickness effects induced by metal confinement. Essentially, the deformation behavior is determined by the mechanical environment induced by metal confinement at the interface. Plastic deformation of both metal and polymer plays an important role in controlling the stress distributions as well as the deformation energetics. The fracture energy of the metal-polyimide interface determined by an overall energy balance method was consistent with that obtained from energy dissipation rate. The average value is 25 J/m2 for the Au/Cr/PMDA-ODA line structure.

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Recent studies on Cu interconnects have shown that interface diffusion between Cu and the cap layer dominates mass transport for electromigration. The kinetics of mass transport by interface diffusion strongly depends on the material and processing of the cap layer. In this series of two papers, we report in Part I the interface and grain-boundary mass transport measured from isothermal stress relaxation in electroplated Cu thin films with and without a passivation layer and in Part II a kinetic model developed to analyze the stress relaxation based on the coupling of grain boundary and interface diffusion. We show that a set of isothermal stress relaxation experiments together with appropriate modeling analysis can be used to evaluate the kinetics of interface and grain-boundary diffusion that correlate to electromigration reliability of Cu interconnects. Thermal stresses in electroplated Cu films with and without passivation, subjected to thermal cycling and isothermal annealing at selected temperatures, were measured using a bending-beam technique. Thermal cycling experiments showed the effect of passivation and provided information to select the initial stresses and temperatures for isothermal stress measurements. Isothermal experiments at moderate temperatures showed a significant transient behavior of stress relaxation. Based on the kinetic model developed in Part II, grain boundary and interface diffusivities were deduced. While the deduced grain boundary diffusivity reasonably agrees with other studies, the diffusivity at the Cu/ SiN cap layer interface was found to be generally lower than the grain-boundary diffusivity at the temperature range of the present study.

Large-area surface ripple structures of indium-tin-oxide films, composed of self-organized nanodots, were induced by femtosecond laser pulses, without scanning. The multi-periodic spacing (~800 nm, ~400 nm and ~200 nm) was observed in the laser-induced ripple of ITO films. The local conductivity of ITO films is significantly higher, by approximately 30 times, than that of the as-deposited ITO films, due to the formation of these nanodots. Such a significant change can be ascribed to the formation of indium metal-like clusters, which appear as budges of ~5 nm height, due to an effective volume increase after breaking the In-O to form In-In bonding.