Semianalytical Modeling of Short-Channel Effects in Lightly Doped Silicon Trigate MOSFETs

Analytical threshold voltage model for lightly doped short-channel tri-gate MOSFETs

“…The threedimensional potential distribution along the channel has been derived in weak inversion based on a perimeter-weighted approach of the potential distributions of the symmetric and asymmetric DG MOSFETs [11]. Following [12], the threshold voltage of the TG MOSFET can be obtained by the superposition of the threshold voltage of the symmetric and asymmetric DG MOSFETs.…”

“…This movement of the most leaky path within the channel cross-section must be taken into account in deriving the drain current equation in short TG FinFETs [14]. Adopting that in TG MOSFETs in weak inversion the most leaky path is located at the middle of the bottom surface of the channel for x = H fin and z = W fin /2 [10] and based on the potential distribution presented in [11], the threshold voltage of the lightly doped symmetric DG MOSFET can be expressed as follows [15]:…”

A 3D analytical modeling of tri-gate tunneling field-effect transistors

“…Recently, to avoid solving for the 3D Poisson's equation that is too difficult to be derived, the 3D potential distribution in TG MOSFETs have been modeled by considering it to be a combination of two independent devices including a symmetric double-gate (SDG) MOSFET and an asymmetric double-gate (ASDG) MOSFET, which results in a good agreement between the numerical solution and analytical expressions [32][33][34][35]. In this way, the resulting analytical potential for the TG devices can be obtained as the perimeter-weighted sum of the analytical potential for the SDG and ASDG devices.…”

“…In this way, the resulting analytical potential for the TG devices can be obtained as the perimeter-weighted sum of the analytical potential for the SDG and ASDG devices. The coupling effects between two DG MOSFETs can be ignored by the restrictions required to obtain operational TG devices that L/W > 2, L/t si > 2 and t box ≥ L [34,35]. Consequently, following the same notion of perimeter-weighted, we consider that the tri-gate TFET device consists of two independent DG TFET, an asymmetric and a symmetric one as shown in Fig.…”

Atomic-scale tomography of semiconductor nanowires

“…Although extraordinary progress has been made, there are still lots of challenges if the performance of chips is expected to have further improvement involving mobility degeneration and further miniaturization [2,3]. However this seems an impossible task with traditional silicon technology due to physical limitation and severe short channel effect (SCE) [4][5][6][7][8][9][10][11][12][13][14][15][16][17][18] as the scaling-down continues.…”