Selective Wet Etching in Fabricating SiGe and Ge Nanowires for Gate-all-Around MOSFETs

Liu, Wen Dar; Lee, Yi–Chia; Sekiguchi, Ryo; Yoshida, Yukifumi; Komori, Kana; Sebaai, Farid; Holsteyns, Frank

doi:10.4028/www.scientific.net/ssp.282.101

Cited by 10 publications

(7 citation statements)

References 6 publications

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“…Wet alkaline solutions such as NH4OH [208] and TMAH [209,210] have a high selectivity in silicon etching to SiGe, but all have obvious crystal orientation, which is due to the etching rate Si (100) > Si (110) > Si (111). Liu et al reported that ACT R 210 and ACT R 301 reduced the crystal orientation behavior of etching and improved the selectivity ratio of Si (111)/SiGe etch to 13: 1 [211]. In order to overcome the wet crystal orientation anisotropy and liquid capillary effect, dry etching is preferred.…”

Section: High Selective Etching For Channel Full Releasementioning

confidence: 99%

State of the Art and Future Perspectives in Advanced CMOS Technology

et al. 2020

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The international technology roadmap of semiconductors (ITRS) is approaching the historical end point and we observe that the semiconductor industry is driving complementary metal oxide semiconductor (CMOS) further towards unknown zones. Today’s transistors with 3D structure and integrated advanced strain engineering differ radically from the original planar 2D ones due to the scaling down of the gate and source/drain regions according to Moore’s law. This article presents a review of new architectures, simulation methods, and process technology for nano-scale transistors on the approach to the end of ITRS technology. The discussions cover innovative methods, challenges and difficulties in device processing, as well as new metrology techniques that may appear in the near future.

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Section: High Selective Etching For Channel Full Releasementioning

confidence: 99%

State of the Art and Future Perspectives in Advanced CMOS Technology

et al. 2020

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“…By a combination of the Si surface modifier and an effective SiGe corrosion inhibitor in ACT ® SG-201, the selectivity of Si (111)/SiGe 25% is significantly improved as compared to the conventional Si etchants. Consequently, ACT ® SG-201 is more efficient in removing the sacrificial Si layer in the Si/SiGe stack [130]. The reduced Si etch rate anisotropy in combination with an effective SiGe corrosion inhibitor prevents SiGe loss during the NW release [130].…”

Section: Etching Evolutionmentioning

confidence: 99%

“…Consequently, ACT ® SG-201 is more efficient in removing the sacrificial Si layer in the Si/SiGe stack [130]. The reduced Si etch rate anisotropy in combination with an effective SiGe corrosion inhibitor prevents SiGe loss during the NW release [130].…”

Section: Etching Evolutionmentioning

confidence: 99%

“…To overcome the anisotropic etch problem in the alkaline solution, isotropic SiGe etch behavior and better Ge protection are required. Different from the Ge etchant with mixtures of HF-H 2 O 2 -H 2 O [135], the formulated solution ACT ® SG-301 employs a selective oxidizer [130], a SiGe etchant, an effective Ge corrosion inhibitor, and a well-designed solvent system for polarity adjustment. By suitable pH control, the oxidized SiGe sacrificial layer could be effectively removed and the Ge NW damage could be minimized [130].…”

Section: Etching Evolutionmentioning

confidence: 99%

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Miniaturization of CMOS

Radamson

Zhang

et al. 2019

Micromachines

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When the international technology roadmap of semiconductors (ITRS) started almost five decades ago, the metal oxide effect transistor (MOSFET) as units in integrated circuits (IC) continuously miniaturized. The transistor structure has radically changed from its original planar 2D architecture to today’s 3D Fin field-effect transistors (FinFETs) along with new designs for gate and source/drain regions and applying strain engineering. This article presents how the MOSFET structure and process have been changed (or modified) to follow the More Moore strategy. A focus has been on methodologies, challenges, and difficulties when ITRS approaches the end. The discussions extend to new channel materials beyond the Moore era.

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“…So far, many studies have proposed Si/SiGe multilayer structures to create an SiGe channel layer [ 17 , 18 , 19 , 20 , 21 ]. In these studies, the solutions of TMAH, mixture solution HF:H 2 O 2 :CH 3 COOH and other alkaline solutions have often been used to obtain a SiGe channel [ 22 , 23 , 24 , 25 ]. However, in the traditional FinFET structure, an important problem is the dry-etching damage to the sidewall caused by plasma sputtering in the fin formation process [ 26 , 27 , 28 , 29 ].…”

Section: Introductionmentioning

confidence: 99%

Strained Si0.2Ge0.8/Ge multilayer Stacks Epitaxially Grown on a Low-/High-Temperature Ge Buffer Layer and Selective Wet-Etching of Germanium

et al. 2020

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With the development of new designs and materials for nano-scale transistors, vertical Gate-All-Around Field Effect Transistors (vGAAFETs) with germanium as channel materials have emerged as excellent choices. The driving forces for this choice are the full control of the short channel effect and the high carrier mobility in the channel region. In this work, a novel process to form the structure for a VGAA transistor with a Ge channel is presented. The structure consists of multilayers of Si0.2Ge0.8/Ge grown on a Ge buffer layer grown by the reduced pressure chemical vapor deposition technique. The Ge buffer layer growth consists of low-temperature growth at 400 °C and high-temperature growth at 650 °C. The impact of the epitaxial quality of the Ge buffer on the defect density in the Si0.2Ge0.8/Ge stack has been studied. In this part, different thicknesses (0.6, 1.2 and 2.0 µm) of the Ge buffer on the quality of the Si0.2Ge0.8/Ge stack structure have been investigated. The thicker Ge buffer layer can improve surface roughness. A high-quality and atomically smooth surface with RMS 0.73 nm of the Si0.2Ge0.8/Ge stack structure can be successfully realized on the 1.2 µm Ge buffer layer. After the epitaxy step, the multilayer is vertically dry-etched to form a fin where the Ge channel is selectively released to SiGe by using wet-etching in HNO3 and H2O2 solution at room temperature. It has been found that the solution concentration has a great effect on the etch rate. The relative etching depth of Ge is linearly dependent on the etching time in H2O2 solution. The results of this study emphasize the selective etching of germanium and provide the experimental basis for the release of germanium channels in the future.

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Selective Wet Etching in Fabricating SiGe and Ge Nanowires for Gate-all-Around MOSFETs

Cited by 10 publications

References 6 publications

State of the Art and Future Perspectives in Advanced CMOS Technology

State of the Art and Future Perspectives in Advanced CMOS Technology

Miniaturization of CMOS

Strained Si0.2Ge0.8/Ge multilayer Stacks Epitaxially Grown on a Low-/High-Temperature Ge Buffer Layer and Selective Wet-Etching of Germanium

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