Strained Si0.2Ge0.8/Ge multilayer Stacks Epitaxially Grown on a Low-/High-Temperature Ge Buffer Layer and Selective Wet-Etching of Germanium

Abstract

With the development of new designs and materials for nano-scale transistors, vertical Gate-All-Around Field Effect Transistors (vGAAFETs) with germanium as channel materials have emerged as excellent choices. The driving forces for this choice are the full control of the short channel effect and the high carrier mobility in the channel region. In this work, a novel process to form the structure for a VGAA transistor with a Ge channel is presented. The structure consists of multilayers of Si0.2Ge0.8/Ge grown on a Ge buffer layer grown by the reduced pressure chemical vapor deposition technique. The Ge buffer layer growth consists of low-temperature growth at 400 °C and high-temperature growth at 650 °C. The impact of the epitaxial quality of the Ge buffer on the defect density in the Si0.2Ge0.8/Ge stack has been studied. In this part, different thicknesses (0.6, 1.2 and 2.0 µm) of the Ge buffer on the quality of the Si0.2Ge0.8/Ge stack structure have been investigated. The thicker Ge buffer layer can improve surface roughness. A high-quality and atomically smooth surface with RMS 0.73 nm of the Si0.2Ge0.8/Ge stack structure can be successfully realized on the 1.2 µm Ge buffer layer. After the epitaxy step, the multilayer is vertically dry-etched to form a fin where the Ge channel is selectively released to SiGe by using wet-etching in HNO3 and H2O2 solution at room temperature. It has been found that the solution concentration has a great effect on the etch rate. The relative etching depth of Ge is linearly dependent on the etching time in H2O2 solution. The results of this study emphasize the selective etching of germanium and provide the experimental basis for the release of germanium channels in the future.

Demonstration of Germanium Vertical Gate-All-Around Field-Effect Transistors Featured by Self-Aligned High-κ Metal Gates with Record High Performance

“…Due to the influence of impurity segregation, B doping forms enrichment or self-doping at the rough interface Ge/Ge 0.8 Si 0.2 , but not at the sharp interface of Ge 0.8 Si 0.2 /Ge. As reported in our previous study, this is because an ordered edge mismatch dislocations (MDs) grid was formed at the interface during the growth process of heterostructures. The edge MDs of the rapidly formed rough Ge/Ge 0.8 Si 0.2 interface are sessile dislocations that cannot slide through the buffer layer to reach the Ge buffer/Si interface .…”

“…As shown in the scanning transmission electron microscopy (STEM) image of Figure a, Ge pVSAFETs were fabricated on 200 mm p-type Si (100) wafers. The high-quality of epitaxial GeSi/Ge/GeSi vertical heterostructure sandwich films, started with a 1.2 μm Ge buffer layer, were grown at 500 °C on Si wafers . Furthermore, the vertical epitaxial sandwich stack consists of a bottom Ge 0.8 Si 0.2 :B doped source layer (on the top of Ge buffer), an undoped Ge channel layer, and an undoped Ge 0.8 Si 0.2 drain layer on the top.…”

“…The high-quality of epitaxial GeSi/Ge/GeSi vertical heterostructure sandwich films, started with a 1.2 μm Ge buffer layer, were grown at 500 °C on Si wafers. 24 Furthermore, the vertical epitaxial sandwich stack consists of a bottom Ge 0.8 Si 0.2 :B doped source layer (on the top of Ge buffer), an undoped Ge channel layer, and an undoped Ge 0.8 Si 0.2 drain layer on the top. The bottom source was doped in situ with boron at a concentration of ∼1 × 10 19 cm −3 during epitaxial growth.…”

“…The epitaxial growth of GeSi/Ge/GeSi vertical heterostructure sandwich films was achieved through reduced pressure chemical vapor deposition (RPCVD, ASM Epsilon 2000) equipment, as shown on our previous study. 24 The 1.2 μm Ge buffer layer was grown at low temperature (Ge seed crystal at 400 °C)/high temperature (Ge film layer at 650 °C). A postgrowth in situ annealing was applied at 820 °C in ambient H 2 to reduce the threading defect density (TDD) below 10 6 cm −2 .…”

Optimization of Structure and Electrical Characteristics for Four-Layer Vertically-Stacked Horizontal Gate-All-Around Si Nanosheets Devices

“…As can be seen from Figure 7 b, the physical L g is 25.8 nm and the stacked GAA Si NSs device is well fabricated, because the SD fin, spacer, and gate trench are well protected with conformal ILD0 material, allowing the Si NS channels and conformal HK/MG GAA structure to be preserved after the final process steps. As can be seen from Figure 7 c, there are four uniform stacked Si NS channels formed and thickness of the NSs is about 6 nm, implying the well-controlled Si NS release and fabrication processes [ 22 , 23 , 24 ]. The Si NSs channel were surrounded by the conformal ALD multilayer HKMG stacks to form GAA structure, which could provide a good gate control ability to the ultrathin Si NS channels.…”