Schottky barrier thin-film transistor (SBTFT) with silicided source/drain and field-induced drain extension

Lin, Horng−Chih; Yeh, Kuo-Liang; Huang, R.G.; Lin, Chun-Hsiung; Huang, Tiao‐Yuan

doi:10.1109/55.915606

Cited by 59 publications

(27 citation statements)

References 9 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…9 The results presented here suggest that SiNW device development will benefit directly from extensive current efforts to find the best gate metals for bulk p-and n-channel MOSFETs. 19,20 In conclusion, we achieved high performance ambipolar SiNW FETs using a two step contact annealing. Single crystalline SiNWs with uniform oxide sheath were prepared by a gas-flow-controlled thermal evaporation method.…”

mentioning

confidence: 79%

Systematic study of contact annealing: Ambipolar silicon nanowire transistor with improved performance

Byon

Tham

Fischer

et al. 2007

Applied Physics Letters

View full text Add to dashboard Cite

High performance ambipolar silicon nanowire (SiNW) transistors were fabricated. SiNWs with uniform oxide sheath thicknesses of 6–7nm were synthesized via a gas-flow-controlled thermal evaporation method. Field effect transistors (FETs) were fabricated using as-grown SiNWs. A two step annealing process was used to control contacts between SiNW and metal source and drain in order to enhance device performance. Initially p-channel devices exhibited ambipolar behavior after contact annealing at 400°C. Significant increases in on/off ratio and channel mobility were also achieved by annealing.

show abstract

mentioning

confidence: 79%

Systematic study of contact annealing: Ambipolar silicon nanowire transistor with improved performance

Byon

Tham

Fischer

et al. 2007

Applied Physics Letters

View full text Add to dashboard Cite

show abstract

“…One method uses a field-induced drain extension [18] located between the channel and the Schottky drain. This leakage current could also be alleviated by using a recessed channel and asymmetric source/drain Schottky contacts [19].…”

Section: Sb Mosfet Simulationmentioning

confidence: 99%

High-Quality Schottky Contacts for Limiting Leakage Currents in Ge-Based Schottky Barrier MOSFETs

Husain

Groot

2009

IEEE Trans. Electron Devices

View full text Add to dashboard Cite

Abstract-Schottky barrier (SB) Ge channel MOSFETs suffer from high drain-body leakage at the required elevated substrate doping concentrations to suppress source-drain leakage. Here, we show that electrodeposited Ni-Ge and NiGe/Ge Schottky diodes on highly doped Ge show low off current, which might make them suitable for SB p-MOSFETs. The Schottky diodes showed rectification of up to five orders of magnitude. At low forward biases, the overlap of the forward current density curves for the as-deposited Ni/n-Ge and NiGe/n-Ge Schottky diodes indicates Fermi-level pinning in the Ge bandgap. The SB height for electrons remains virtually constant at 0.52 eV (indicating a hole barrier height of 0.14 eV) under various annealing temperatures. The series resistance decreases with increasing annealing temperature in agreement with four-point probe measurements indicating the lower specific resistance of NiGe as compared to Ni, which is crucial for high drive current in SB p-MOSFETs. We show by numerical simulation that by incorporating such high-quality Schottky diodes in the source/drain of a Ge channel PMOS, a highly doped substrate could be used to minimize the sourceto-drain subthreshold leakage current.

show abstract

“…The key idea of the new design is to have large electric fields at the source contact but small fields at the drain, to suppress unwanted tunneling. A related approach has recently been demonstrated for Si-based SB-FETs 9 . For an ambipolar SB-CNFET, the asymmetric design can suppress either the p-or the n-type branch of the ambipolar transport characteristic, depending only on the sign of the drain voltage.…”

mentioning

confidence: 99%

Electrostatic engineering of nanotube transistors for improved performance

Heinze

Tersoff

Avouris

2003

Applied Physics Letters

View full text Add to dashboard Cite

With decreasing device dimensions, the performance of carbon nanotube field-effect transistors (CNFETs) is limited by high Off currents except at low drain voltages. We show that an asymmetric design improves the performance, reducing Off-currents and extending the usable range of drain voltage. The improvement is most dramatic for ambipolar Schottky-barrier CNFETs. Moreover, this approach allows a single device to exhibit equally good performance as an n-or p-type transistor, by changing only the sign of the drain voltage. Even for CNFETs having ohmic contacts, an asymmetric design can greatly improve the performance for small-bandgap nanotubes.The performance of carbon nanotube field-effect transistors (CNFETs) can be greatly improved in many respects by scaling the devices to smaller size 1-4 . However, the improvements with smaller size are accompanied by the undesired effect of a lowered On-Off ratio at typical drain voltages. This restricts the range of usable drain voltage, which in turn limits the achievable On-currents. Most CNFETs to date operate as Schottky barrier (SB) CNFETs 1-7 , and the issue has been studied in detail for such devices 7,8 . But the problem occurs even for ohmic contacts, especially for small-bandgap tubes, as shown below.Here, we propose a novel device design for CNFETs that can be scaled down in size for good turn-on performance without severe restrictions on the usable drain voltage. The key idea of the new design is to have large electric fields at the source contact but small fields at the drain, to suppress unwanted tunneling. A related approach has recently been demonstrated for Si-based SB-FETs 9 . For an ambipolar SB-CNFET, the asymmetric design can suppress either the p-or the n-type branch of the ambipolar transport characteristic, depending only on the sign of the drain voltage. Thus the same device can act as an excellent p-or n-type transistor, and the turn-on performance for both types is controlled by the electrostatics (the geometry of the contact and gate) at the source electrode. By choosing metals of different work function for the gates, it should be possible to fabricate complementary SB-CNFETs that have the desired alignment of transfer characteristics (I vs. V g ) for standard logic applications.For a SB-CNFET, the asymmetric design solves the problem of Off-current that increases exponentially with drain voltage, so it allows larger On-currents. This is a critical issue as the device dimensions decrease 7,8 . Moreover, even for a CNFET having ohmic contacts 10 , e.g. to the valence band, suppressing the current into the conduction band can be essential when the nanotube (NT) bandgap is small.Two examples of possible asymmetric device geometries are shown in Fig.

show abstract

Schottky barrier thin-film transistor (SBTFT) with silicided source/drain and field-induced drain extension

Cited by 59 publications

References 9 publications

Systematic study of contact annealing: Ambipolar silicon nanowire transistor with improved performance

Systematic study of contact annealing: Ambipolar silicon nanowire transistor with improved performance

High-Quality Schottky Contacts for Limiting Leakage Currents in Ge-Based Schottky Barrier MOSFETs

Electrostatic engineering of nanotube transistors for improved performance

Contact Info

Product

Resources

About