Scaling limit for InGaAs/GaAsSb heterojunction double-gate tunnel FETs from the viewpoint of direct band-to-band tunneling from source to drain induced off-characteristics deterioration

Lin, Wenbo; Iwata, Shinjiro; Fukuda, Koichi; Miyamoto, Yasuyuki

doi:10.7567/jjap.55.070303

Cited by 4 publications

(5 citation statements)

References 23 publications

(24 reference statements)

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“…It can be seen that when L CH is 25 nm, the sub-threshold slope is dull and I ON has decreased. 25) This effect occurs when the tunneling current flows directly between the source and drain when L CH = 25 nm and I OFF increases. Figure 10 shows the energy band profile and the BTBT generation rate at V from the source to the drain along the center of the device.…”

Section: Device Optimizationmentioning

confidence: 99%

“…[6][7][8][9][10][11] Among these steep switching devices, the tunnel FET is a promising alternative to CMOS and has been studied extensively both experimentally [12][13][14][15][16][17][18][19][20][21] and theoretically. [22][23][24][25][26][27][28] Despite aiming for steep switching, most studies on TFETs face the challenge of TFETs not being steep due to the lack of on-current or high off-current. In terms of on-current, a direct bandgap III-V semiconductor with a light tunnel mass is a promising alternative.…”

Section: Introductionmentioning

confidence: 99%

“…For example, a theoretical study states that if the channel length is shortened, the steepness of switching is lost due to direct tunneling from the source to the drain. 25) When the body thickness is reduced, the effective band gap increases due to the quantum effect, causing the tunnel current to decrease.…”

Section: Introductionmentioning

confidence: 99%

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Circuit speed oriented device design scheme for GaAsSb/InGaAs double-gate hetero-junction tunnel FETs

Fukuda

Nogami

Kunisada

et al. 2020

Jpn. J. Appl. Phys.

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This study investigated the device optimization scheme of a double-gate hetero-junction tunnel FET, which was expected to improve circuit performance. A thinner channel with a stronger electric field increases the tunnel on-current. Conversely, a thin channel results in a larger quantum sub-band energy and an effective bandgap, which decreases the tunnel on-current. Such tradeoffs are clarified by considering the quantum effects in a device simulation. Furthermore, the gate capacitance behavior, identified via device simulation, was considered, and it demonstrates that the double-gate hetero-junction tunnel FET has a substantial capacitance merit compared to CMOS transistors. The early stages of our work used the intrinsic delay for device optimization, as defined in the international technology roadmap for semiconductors. However, based on the comparison with the speed evaluation results of the ring oscillator, the device optimization scheme was improved. This was achieved by adopting a new effective delay index, based on the effective on-currents and effective gate capacitances. Studies on the CMOS device design also applied the concept of effective on-current; however, the design method presented herein is novel in that it introduced the concept of effective gate capacitance.

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Section: Device Optimizationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Circuit speed oriented device design scheme for GaAsSb/InGaAs double-gate hetero-junction tunnel FETs

Fukuda

Nogami

Kunisada

et al. 2020

Jpn. J. Appl. Phys.

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“…[6][7][8][9][10][11] Among them, tunnel field-effect transistors (TFETs) have been most extensively studied, both experimentally [12][13][14][15][16][17][18][19][20] and theoretically. [21][22][23][24][25][26][27] Most of those TFETs were designed for realizing larger on-currents, smaller off-currents, and steep subthreshold slopes. On the other hand, short-channel effects (SCEs) of TFETs have not received sufficient attention, with only a few studies addressing this issue.…”

Section: Introductionmentioning

confidence: 99%

Simulation study of short-channel effects of tunnel field-effect transistors

Fukuda

Asai

Hattori

et al. 2018

Jpn. J. Appl. Phys.

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Short-channel effects of tunnel field-effect transistors (FETs) are investigated in detail using simulations of a nonlocal band-to-band tunneling model. Discussion is limited to silicon. Several simulation scenarios were considered to address different effects, such as source overlap and drain offset effects. Adopting the drain offset to suppress the drain leakage current suppressed the short channel effects. The physical mechanism underlying the short-channel behavior of the tunnel FETs (TFETs) was very different from that of metal–oxide–semiconductor FETs (MOSFETs). The minimal gate lengths that do not lose on-state current by one order are shown to be 3 nm for single-gate structures and 2 nm for double gate structures, as determined from the drain offset structure.

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“…One promising candidate is the Tunnel Field-Effect Transistor (TFET), which uses quantum mechanical tunneling to filter the injected carriers rather than thermal emission [1,2]. The general development in the field has generated devices that either demonstrate operation well below the thermal limit at low currents [3][4][5] or operate at useful currents without ability to reach slopes well below the thermal limit [6][7][8][9][10][11]. Vertical nanowire InAs/InGaAsSb/GaSb TFETs have recently demonstrated promising performance with ability to combine operation below the thermal limit with technically useful currents [12,13].…”

Section: Introductionmentioning

confidence: 99%