Simulation study of short-channel effects of tunnel field-effect transistors

Abstract

Short-channel effects of tunnel field-effect transistors (FETs) are investigated in detail using simulations of a nonlocal band-to-band tunneling model. Discussion is limited to silicon. Several simulation scenarios were considered to address different effects, such as source overlap and drain offset effects. Adopting the drain offset to suppress the drain leakage current suppressed the short channel effects. The physical mechanism underlying the short-channel behavior of the tunnel FETs (TFETs) was very different from that of metal–oxide–semiconductor FETs (MOSFETs). The minimal gate lengths that do not lose on-state current by one order are shown to be 3 nm for single-gate structures and 2 nm for double gate structures, as determined from the drain offset structure.

Mechanism of extraordinary gate-length dependence of quantum dot operation in isoelectronic-trap-assisted tunnel FETs

“…In conventional silicon TFET operation, the current characteristics are almost independent of L G because the tunneling current flows at the source-edge. 20) Therefore, it is speculated that dot-intermediated tunneling also occurs at the source-edge and that the Coulomb blockade transport does not depend on L G . However, this speculation is not consistent with the experimental results.…”