Circuit speed oriented device design scheme for GaAsSb/InGaAs double-gate hetero-junction tunnel FETs

Abstract

This study investigated the device optimization scheme of a double-gate hetero-junction tunnel FET, which was expected to improve circuit performance. A thinner channel with a stronger electric field increases the tunnel on-current. Conversely, a thin channel results in a larger quantum sub-band energy and an effective bandgap, which decreases the tunnel on-current. Such tradeoffs are clarified by considering the quantum effects in a device simulation. Furthermore, the gate capacitance behavior, identified via device simulation, was considered, and it demonstrates that the double-gate hetero-junction tunnel FET has a substantial capacitance merit compared to CMOS transistors. The early stages of our work used the intrinsic delay for device optimization, as defined in the international technology roadmap for semiconductors. However, based on the comparison with the speed evaluation results of the ring oscillator, the device optimization scheme was improved. This was achieved by adopting a new effective delay index, based on the effective on-currents and effective gate capacitances. Studies on the CMOS device design also applied the concept of effective on-current; however, the design method presented herein is novel in that it introduced the concept of effective gate capacitance.

Calculation of GaInSb PNP lateral HBT for complementary bipolar logic technology

“…In general, in the case of complementary circuits, similar characteristics are preferred for NPN and PNP transistors. Thus, for circuit analysis, we assumed that the polarity-reversed characteristics 12) of the PNP-lateral HBTs were NPN HBTs.…”