Run-Time Management of a MPSoC Containing FPGA Fabric Tiles

Nollet, V.; Avasare, Prabhat; Eeckhaut, Hendrik; Verkest, D.; Corporaal, Henk

doi:10.1109/tvlsi.2007.912097

Cited by 49 publications

(25 citation statements)

References 7 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In this work, the authors propose to divide the entire reconfigurable area into identical tiles, connected among them by an interconnection network (ICN). Recently Nollet et al [10] have proposed to extend this approach applying the idea of configuration hierarchy to build a reconfigurable Multi-Processor System-on-a-Chip (MPSoC). Basically, instead of executing dedicated HW tasks in the reconfigurable resources, they use these resources to implement programmable softcores that will execute SW tasks.…”

Section: Related Workmentioning

confidence: 99%

“…The objective of this process is to find a schedule that provides the same performance than ref_sch, but with the minimum number of tasks assigned to CT. We initialize CT as empty (line 3) and we start an iterative process (lines [5][6][7][8][9][10][11][12]. The while loop starts computing a new schedule (current_sch, line 6) and compares its execution time with the execution time of ref_sch (line 7).…”

Section: ) Critical Tasks Identificationmentioning

confidence: 99%

See 1 more Smart Citation

A Hardware Implementation of a Run-Time Scheduler for Reconfigurable Systems

Clemente

Resano

González

et al. 2011

IEEE Trans. VLSI Syst.

View full text Add to dashboard Cite

Abstract-New generation embedded systems demand high performance, efficiency and flexibility. Reconfigurable hardware can provide all these features. However the costly reconfiguration process and the lack of management support have prevented a broader use of these resources. To solve these issues we have developed a scheduler that deals with task-graphs at run-time, steering its execution in the reconfigurable resources while carrying out both prefetch and replacement techniques that cooperate to hide most of the reconfiguration delays. In our scheduling environment task-graphs are analyzed at design-time to extract useful information. This information is used at run-time to obtain near-optimal schedules, escaping from local-optimum decisions, while only carrying out simple computations. Moreover, we have developed a hardware implementation of the scheduler that applies all the optimization techniques while introducing a delay of only a few clock cycles. In the experiments our scheduler clearly outperforms conventional run-time schedulers based on As-Soon-As-Possible techniques. In addition, our replacement policy, specially designed for reconfigurable systems, achieves almost optimal results both regarding reuse and performance.

show abstract

Section: Related Workmentioning

confidence: 99%

Section: ) Critical Tasks Identificationmentioning

confidence: 99%

A Hardware Implementation of a Run-Time Scheduler for Reconfigurable Systems

Clemente

Resano

González

et al. 2011

IEEE Trans. VLSI Syst.

View full text Add to dashboard Cite

show abstract

“…To overcome the shortcomings of pure static [4,11,15] and dynamic [21,36] task mapping algorithms, hybrid (semi-static) approaches have become increasingly popular in recent years. Usually, in this kind of approaches, multiple mapping solutions are found at design time and applied at run time based on the current state of the system.…”

Section: Scalable Run-time Task Mapping In Sharamentioning

confidence: 99%

A hierarchical run-time adaptive resource allocation framework for large-scale MPSoC systems

Quan

Pimentel

2016

Des Autom Embed Syst

View full text Add to dashboard Cite

In the embedded computer system domain, MPSoC systems have become increasingly popular due to the ever-increasing performance demands of modern embedded applications. The number of processing elements in these MPSoCs also steadily increases. Whereas current MPSoCs still contain a limited number of processing elements, future MPSoCs will feature tens up to hundreds of (heterogeneous) processing elements that are all integrated on a single chip. On these future large-scale MPSoC systems, the mapping of applications onto the hardware resources plays an important role to fully explore the parallelism of applications. In this article, a hierarchical run-time adaptive resource allocation framework which uses an intelligent task remapping approach is proposed to improve the system performance for large-scale MPSoCs.

show abstract

“…This is done to avoid a lot of resource reservation which results in a huge overhead on the mapping algorithm. Nollet et al [3] investigate a run-time task assignment heuristic in a multiprocessor SoC containing fine-grain reconfigurable hardware tiles. While they have considered fully reconfigurable FPGAs in a heterogeneous multi-processor The authors acknowledge with gratitude the support obtained from the EPSRC UK under grant number EP/E062164/1 SoC, in this work we consider the partial run-time reconfigurable feature of FPGAs.…”

Section: Related Workmentioning

confidence: 99%

Run-time resource management in fault-tolerant network on reconfigurable chips

Hosseinabady

Nunez-Yanez

2009

2009 International Conference on Field Programmable Logic and Applications

View full text Add to dashboard Cite

This paper investigates the challenges of run-time resource management in future coarse-grained network-onreconfigurable-chips (NoRCs). Run-time reconfiguration is a key feature expected in future processing systems which must support multiple applications whose processing requirements are not known at design time. This paper investigates a stochastic routing algorithm in a NoC-based system with dynamically reconfigurable tiles, able to cope with the dynamic behaviour of run-time task mapping. Experimental results show the efficiency of the proposed stochastic task mapping.

show abstract

Run-Time Management of a MPSoC Containing FPGA Fabric Tiles

Cited by 49 publications

References 7 publications

A Hardware Implementation of a Run-Time Scheduler for Reconfigurable Systems

A Hardware Implementation of a Run-Time Scheduler for Reconfigurable Systems

A hierarchical run-time adaptive resource allocation framework for large-scale MPSoC systems

Run-time resource management in fault-tolerant network on reconfigurable chips

Contact Info

Product

Resources

About