A Hardware Implementation of a Run-Time Scheduler for Reconfigurable Systems

Clemente, Juan Antonio; Resano, Javier; González, Carlos Villaseca; Mozos, Daniel

doi:10.1109/tvlsi.2010.2050158

Cited by 41 publications

(53 citation statements)

References 21 publications

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“…In addition, it is assumed that task graphs are soft real-time, that decreasing makespan leads to increasing Quality of Service (QoS) [7], such as the H.264 video encoder [24].…”

Section: A Task Modelmentioning

confidence: 99%

“…GS stands for CLB group size (in terms of CLB count in each group), and finally CD is the configuration delay of a CLB group. The configurations are carried out in a serial manner [7]. For practical reasons, it has been assumed that the tasks are reconfigured in the target device following a 1D reconfiguration model.…”

Section: B Reconfigurable Computer Modelmentioning

confidence: 99%

“…To manage the execution of hardware task graphs, since list-based scheduling techniques need little computation time and provide sub-optimal but good schedules [7], the proposed solution uses a non-preemptible As Soon As Possible (ASAP) scheduler. Thus, first of all, the Starting Configuration Time (SCT (τ i )) of Task τ i is determined taking into account the tasks' precedence constraints as follows:…”

Section: Scheduling Modelmentioning

confidence: 99%

“…These devices can be reconfigured multiple times at run-time, which makes a single FPGA capable of executing multiple functionalities in a time-multiplexed manner. This feature allows executing hardware task graphs whose size is bigger than the FPGA, by employing appropriate scheduling techniques [7].…”

mentioning

confidence: 99%

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Reliability and Makespan Optimization of Hardware Task Graphs in Partially Reconfigurable Platforms

Ramezani

Sedaghat

Naghibzadeh

et al. 2017

IEEE Trans. Aerosp. Electron. Syst.

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Abstract-This paper addresses the problem of reliability and makespan optimization of hardware task graphs in reconfigurable platforms by applying fault tolerance (FT) techniques to the running tasks based on the exploration of the Pareto set of solutions. In the presented solution, in contrast to existing approaches in the literature, task graph scheduling, tasks parallelism, reconfiguration delay, and FT requirements are taken into account altogether. This paper firstly presents a model for hardware task graphs, task prefetch and scheduling, reconfigurable computer and a fault model for reliability. Then, a mathematical model of an integer nonlinear multi-objective optimization problem is presented for improving the FT of hardware task graphs, scheduled in partially reconfigurable platforms. Experimental results show the positive impacts of choosing the FT techniques selected by the proposed solution, which is named Pareto-based. Thus, in comparison to non-fault-tolerant designs or other stateof-the-art FT approaches, without increasing makespan, about 850% Mean Time To Failure (MTTF) improvement is achieved and, without degrading reliability, makespan is improved by 25%. In addition, experiments in fault-varying environments have demonstrated that the presented approach outperforms existing state-of-the-art adaptive FT techniques in terms of both MTTF and makespan.

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“…In addition, it is assumed that task graphs are soft real-time, that decreasing makespan leads to increasing Quality of Service (QoS) [7], such as the H.264 video encoder [24].…”

Section: A Task Modelmentioning

confidence: 99%

Section: B Reconfigurable Computer Modelmentioning

confidence: 99%

Section: Scheduling Modelmentioning

confidence: 99%

mentioning

confidence: 99%

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Reliability and Makespan Optimization of Hardware Task Graphs in Partially Reconfigurable Platforms

Ramezani

Sedaghat

Naghibzadeh

et al. 2017

IEEE Trans. Aerosp. Electron. Syst.

Self Cite

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show abstract

“…Most of the circuit relocation systems present in the literature still demand that identical location(s) must exist on chip before any form of circuit relocation is possible [5] [7] [8] [9] [10]. They address only direct bitstream placement and relocation and do not provide any means of relocating circuits to non-identical locations.…”

Section: Introduction and Related Workmentioning

confidence: 99%

A Functionality-Based Runtime Relocation System for Circuits on Heterogeneous FPGAs

Enemali

Adetomi

Seetharaman

et al. 2018

IEEE Trans. Circuits Syst. II

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Abstract-Runtime Relocation of circuits on FPGAs have beenproposed for achieving many desirable features including fault tolerance, defragmentation and system load balancing. However, the changes in the architectural composition of FPGAs has made relocation more challenging mainly because FPGAs have become more heterogeneous. Previous and state-of-the-art circuit relocation systems on FPGAs have relied only on direct bitstream relocation which requires the source and destination resource layouts to be the same, as well as access to the design bitstream for manipulation. Hence, their efficiency on modern heterogeneous chips greatly reduces, and mostly cannot be applied to encrypted bitstreams of intellectual property (IP) blocks. In this paper, we present a circuit relocator which augments direct bitstream relocation with a functionalitybased relocation scheme. We demonstrate the feasibility of the proposed technique using a CORDIC application and show that an average of over 2.6-fold increase in number of relocations can be obtained compared to only direct bitstream relocation at expense of a small memory overhead and manageable relocation time for this case study.

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Algorithms for reducing reconfiguration overheads using prefetch, reuse, and optimal mapping of tasks

Hariharan

Kannan

2018

Concurrency and Computation

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Summary Field Programmable Gate Arrays (FPGAs) are preferred in the modern embedded system to accelerate the performance of the entire system. However, the FPGAs are liable to suffer from reconfiguration overheads. These overheads are mainly because of the configuration data being fetched from the off‐chip memory at run‐time and due to the improper management of tasks during execution. To reduce these overheads, two algorithms are proposed. Both the algorithms focus on the prefetch heuristics, reuse technique, and an optimal mapping of tasks over the available memories. However, in terms of reusing technique, algorithm‐1 uses least recently used (LRU) policy and algorithm‐2 uses the optimal replacement policy (considering the vitality of the reconfigurable units (RUs)). Simulation results are obtained for both the algorithms. It is evident from the result that most of the reconfiguration overheads are eliminated when the applications are managed and executed based on the proposed algorithms. Also, the two algorithm results are compared and analyzed. For this purpose, the experiments included smaller and larger task graphs. In the case of smaller task graphs, algorithm‐2 outperforms algorithm‐1 in reducing reconfiguration overheads. In larger task graphs, algorithm‐1 produces better results compared to algorithm‐2.

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A Hardware Implementation of a Run-Time Scheduler for Reconfigurable Systems

Cited by 41 publications

References 21 publications

Reliability and Makespan Optimization of Hardware Task Graphs in Partially Reconfigurable Platforms

Reliability and Makespan Optimization of Hardware Task Graphs in Partially Reconfigurable Platforms

A Functionality-Based Runtime Relocation System for Circuits on Heterogeneous FPGAs

Algorithms for reducing reconfiguration overheads using prefetch, reuse, and optimal mapping of tasks

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