ROUTABILITY-DRIVEN PACKING: METRICS AND ALGORITHMS FOR CLUSTER-BASED FPGAs

Abstract

Most of the FPGA's area and delay are due to routing. Considering routability at earlier steps of the CAD flow would both yield better quality and faster design process. In this paper, we discuss the metrics that affect routability in packing logic into clusters. We are presenting a routability-driven clustering method for cluster-based FPGAs. Our method packs LUTs into logic clusters while incorporating routability metrics into a cost function. Based on our routability model, the routability in timing-driven packing algorithm is analyzed. We integrate our routability model into a timing-driven packing algorithm. Our method yields up to 50% improvement in terms of the minimum number of routing tracks compared to VPack (16.5% on average). The average routing area improvement is 27% over VPack and 12% over t-VPack.

Power Efficient Data-Aware SRAM Cell for SRAM-Based FPGA Architecture

“…The gating technique has been successfully used in ASICs, but it is not very effective in SRAM-based FPGAs because a large component of power consumption in FPGA is due to the switching activities of the clock signals along the routing switches. For this reason, researchers investigated the possibility of modifying the way a circuit is mapped on the FPGA array by acting on the synthesis, technology mapping, or placement and routing algorithms [66,67]. Since clock is distributed in the chip through the global FPGA routing network, the placement of clock loads has a considerable impact on clock wire usage.…”

Timing-Driven Nonuniform Depopulation-Based Clustering

“…Power-driven Timing-driven Routability-driven P-T-VPack, [18] SMAC, [12] SCPlace, [10] T-VPack, [4] T-RPack, [9] HDPack, [13] Marrakchi et al [11] * Target less than max logic utilization: "depopulated" CLBs Uniform depopulation * Non-uniform depopulation * T-NDPack Un/DoPack, [3] Tom and Lemieux [7] iRac, [5] Tessier and Giza [6] Figure 1: Categorization of clustering techniques based on logic utilization approach and optimization goals.…”

“…Therefore if few available BLEs are left in a CLB and related block is not available, it is wiser to leave the BLEs unused. Typically, clustering techniques modify the cost function ( [4,5,9]) or the algorithm flow [10] or both ( [11][12][13]). Here we summarize in what capacity the well-known approaches enhance the clustering flow and highlight where our approach stands relative to them.…”

“…T-RPack [9] uses the same algorithm flow as T-VPack and modifies the cost function. T-RPack modifies the routability part in the cost function by taking into account the individual contributions of both shared and nonshared nets between the CLB under construction and the block under consideration.…”

“…For (each benchmark) (5) Run T-NDPack to obtain the number of used CLBs (6) Run VPR to obtain the minimum channel width and critical path delay (7) End for (8) Caculate the average number of used CLBs, minimum channel width and critical path delay (9) End for (10) End for (11) End for Algorithm 2: Experiments for identifying best configuration values for α, MUT, and CBT (note that UBT is set to be 4).…”