Clustering technique to reduce chip area and delay for FPGA

Abstract

SUMMARYIn this paper, we study the requirements for electronic design automation (EDA) tools in deep-submicron technologies and identify critical factors for programmable logic devices. We also propose a clustering technique for a cluster-based FPGA to optimize routability of outer cluster nets. In order to reduce the routing resources used in FPGA, this technique uses two evaluation functions. One evaluation function reduces the routing resources in the outer cluster. The second evaluation function utilizes various characteristics of the local routing resources in the inner cluster. Our clustering technique has the unique ability to optimize routing resources concurrently. As a result, the area is decreased by 13.5%, and the delay is reduced by 9.3% as compared to the latest clustering tool in benchmark circuits.

Beyond the arithmetic constraint: depth-optimal mapping of logic chains in reconfigurable fabrics

“…Other clustering approaches deviate from the cluster-seed model through the use of more complex approaches. The tool presented in [47] aims to consider intra-cluster and intercluster resources separately, and then combine these factors to in an overall cost function.…”

“…It should be noted that all of the results in Table 6.3 are based on K = 4, N = 8, and in most cases I = 18 ([47] uses I = 32). Additionally, RT-Pack results obtained from [47] (thus using I = 32) concur with those in [15] and are included because they present wire length.…”