Beyond the arithmetic constraint: depth-optimal mapping of logic chains in reconfigurable fabrics

Somani, Arun K.; Frederick, M.T.

doi:10.31274/rtd-180813-16975

Cited by 7 publications

(10 citation statements)

References 36 publications

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“…In particular, they are not capable of inverting the incoming carry. This is the very limitation hindering the automated carry-chain mapping by Frederick and Somani [8] to be used for such target devices.…”

Section: Carry Chainsmentioning

confidence: 99%

“…Another use was demonstrated for token-based arbitration schemes [7], which, however, require a device-specific, low-level design to achieve such a mapping. An automated mapping of deep logic chains to carry chains was described by Frederick and Somani [8]. Unfortunately, their algorithm assumes carry-chain links that are fed from programmable lookup table (LUT) outputs.…”

Section: Related Workmentioning

confidence: 99%

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Mapping basic prefix computations to fast carry-chain structures

Preußer

Spallek

2009

2009 International Conference on Field Programmable Logic and Applications

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Carry chains are a standard feature of modern FPGA architectures. They enable compact, regular and yet very fast implementations of the binary word addition even outpacing sophisticated parallel prefix networks for bit width far beyond 100. Although they are equally suited for other simple prefix computations, their employment in the implementation of such user functions is hindered by unportable lowlevel and vendor-or even device-specific means to implement the desired mapping. This paper names suitable example applications, identifies the class of prefix computations generically mappable to carry chains and presents a universal procedure to achieve this mapping by a transformation building upon the well-supported binary word addition. Synthesis results are presented to illustrate both the gain in speed and the significant reduction of area through the employment of this approach.

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Section: Carry Chainsmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Mapping basic prefix computations to fast carry-chain structures

Preußer

Spallek

2009

2009 International Conference on Field Programmable Logic and Applications

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show abstract

“…However, when the arithmetic operations are described at gate-level, state-of-the-art tools often miss opportunities to use carry chains, even for circuits rich in adder logic composed of 3-input majority functions and 3-input XOR gates, for which using the carry chains could reduce both area and delay. Frederick and Somani [3] proposed a mapping algorithm that exploits carry chains for general circuits, proving that carry chains have the potential to improve the delay of general-purpose circuits and not only arithmetic circuits. However, this technique is only applicable to carry-select chains, which are no longer present in modern FPGAs, whereas ours detects only ripple-carry chains but can map the resulting adders on any hardened adder structure, as discussed in Section III.…”

Section: Related Workmentioning

confidence: 99%

Improved carry chain mapping for the VTR flow

Petkovska

Zgheib

Novo

et al. 2015

2015 International Conference on Field Programmable Technology (FPT)

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Carry chains facilitate the implementation of adders and improve the performance of arithmetic circuits in FPGAs. The last version of the commonly used open-source Verilog-toRouting (VTR) CAD flow now enables modelling carry chains in FPGA architectures. However, one of the shortcomings of the existing flow lies in its inability to identify arithmetic operations when described as gate-level circuits. Moreover, the VTR flow squanders most of the LUTs preceding the chain logic. This paper focuses on these two problems and proposes preprocessing the circuit before technology mapping to allow for a more efficient use of carry chains. The first proposed method maps logic on the carry chains for circuits expressed using a gate-level description. On average, it identifies about 30% more meaningful full adders than the existing tool flow operating on the RTL descriptions. Area is thus improved by up to 15% with an average of 6% for almost no delay penalty. Secondly, we increase the use of the LUTs preceding the chain logic by a factor 2 on average. This reduces delay (up to 9%) and area (up to 2%), compared to the existing VTR flow. The new approach is independent of the specific carry-chain architecture and can be generically adapted to any FPGA with built-in hardened adders.

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“…The ChainMap algorithm attempts to map arbitrary logic functions onto the carry chain of the Altera Stratix and Cyclone FPGAs [16]; as mentioned above, this carry chain has been deprecated and the authors readily admit that their algorithm is not applicable to newer Altera FPGAs or Xilinx FPGAs. Our chaining heuristic does share some principle similarities with ChainMap, but targets the logic chain that we have proposed rather than carry chains.…”

Section: Related Workmentioning

confidence: 99%

Reducing the pressure on routing resources of FPGAs with generic logic chains

Parandeh-Afshar

Zgheib

Brisk

et al. 2011

Proceedings of the 19th ACM/SIGDA International Symposium on Field Programmable Gate Arrays

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Routing resources in modern FPGAs use 50% of the silicon real estate and are significant contributors to critical path delay and power consumption; the situation gets worse with each successive process generation, as transistors scale more effectively than wires. To cope with these challenges, FPGA architects have divided wires into local and global categories and introduced fast dedicated carry chains between adjacent logic cells, which reduce routing resource usage for certain arithmetic circuits (primarily adders and subtractors).Inspired by the carry chains, we generalize the idea to connect lookup tables (LUTs) in adjacent logic cells. By exploiting the fracturable structure of LUTs in current FPGA generations, we increase the utilization of the existing LUTs in the logic cell by providing new inputs along the logic chain, but without increasing the I/O bandwidth from the programmable interconnect. This allows us to increase the logic density of the configurable logic cells while reducing demand for routing resources, as long as the mapping tools are able to exploit the logic chains. Our experiments using the combinational MCNC benchmarks and comparing against an Altera Stratix-III FPGA show that the introduction of logic chains reduce the average usage of local routing wires by 37%, with a 12% reduction in total wiring (local and global); this translates to improvements in dynamic power consumption of 18% in the routing network and 10% overall, while utilizing 4% fewer logic cells, on average.

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Beyond the arithmetic constraint: depth-optimal mapping of logic chains in reconfigurable fabrics

Cited by 7 publications

References 36 publications

Mapping basic prefix computations to fast carry-chain structures

Mapping basic prefix computations to fast carry-chain structures

Improved carry chain mapping for the VTR flow

Reducing the pressure on routing resources of FPGAs with generic logic chains

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