Robustness of SiC MOSFET under avalanche conditions

Dchar, Ilyas; Zolkos, Marion; Buttay, Cyril; Morel, Hervé

doi:10.1109/apec.2017.7931015

Cited by 24 publications

(12 citation statements)

References 8 publications

(9 reference statements)

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“…As a thermally sensitive metric, E AVA highly relies on t AVA as T j depends on the heating/cooling process. Tested at the similar t AVA , state-of-the-art SiC MOSFETs showed an E AVA density of 6-15 J/cm 2 [38], [39]. The comparable E AVA density values in GaN FinFETs and SiC MOSFETs manifest the excellent avalanche robustness of the vertical GaN Fin-JFET.…”

Section: Uis Testmentioning

confidence: 87%

1.2-kV Vertical GaN Fin-JFETs: High-Temperature Characteristics and Avalanche Capability

Liu

Xiao

Zhang

et al. 2021

IEEE Trans. Electron Devices

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This work describes the high-temperature performance and avalanche capability of normally-OFF 1.2-kV-class vertical gallium nitride (GaN) fin-channel junction field-effect transistors (Fin-JFETs). The GaN Fin-JFETs were fabricated by NexGen Power Systems, Inc. on 100-mm GaN-on-GaN wafers. The threshold voltage (V TH) is over 2 V with less than 0.15 V shift from 25 • C to 200 • C. The specific ON-resistance (R ON) increases from 0.82 at 25 • C to 1.8 m•cm 2 at 200 • C. The thermal stability of V TH and R ON are superior to the values reported in SiC MOSFETs and JFETs. At 200 • C, the gate leakage and drain leakage currents remain below 100 μA at −7-V gate bias and 1200-V drain bias, respectively. The gate leakage current mechanism is consistent with carrier hopping across the lateral p-n junction. The high-bias drain leakage current can be well described by the Poole-Frenkel (PF) emission model. An avalanche breakdown voltage (BV AVA) with positive temperature coefficient is shown in both the quasistatic I-V sweep and the unclamped inductive switching (UIS) tests. The UIS tests also reveal a BV AVA over 1700 V and a critical avalanche energy (E AVA) of 7.44 J/cm 2 , with the E AVA comparable to that of state-of-the-art SiC MOSFETs. These results show the great potentials of vertical GaN Fin-JFETs for medium-voltage power electronics applications.

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Section: Uis Testmentioning

confidence: 87%

1.2-kV Vertical GaN Fin-JFETs: High-Temperature Characteristics and Avalanche Capability

Liu

Xiao

Zhang

et al. 2021

IEEE Trans. Electron Devices

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“…This is because the failure in the simulation model occurs globally, while in reality, only a specific area of the MOSFET device is broken. 5,11,12,32) The heat and current concentration within that local area increase the temperature (and thus the current) even further in the measurement.…”

Section: Validation Of the Proposed Modelmentioning

confidence: 99%

“…The main causes of failures in the UIS test are considered to be either 1) the activation of a parasitic bipolar junction transistor (BJT), or 2) the intrinsic operation of SiC. 5,7,8,[10][11][12][13] The parasitic BJT is located at the NPN junction near the channel, as shown in Fig. 2.…”

Section: Introductionmentioning

confidence: 99%

An electrothermal compact model of SiC MOSFETs for analyzing avalanche failure mechanisms

Shimozato

Nakamura

Bian

et al. 2021

Jpn. J. Appl. Phys.

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Avalanche failure that occurs in circuits with inductive loads is an important issue facing silicon carbide (SiC) metal–oxide–semiconductor field-effect transistors (MOSFETs). Two mechanisms have been suggested for this failure: the activation of a parasitic bipolar junction transistor (BJT), and the intrinsic operation of SiC at extremely high temperatures. In this study, we propose a SPICE-based electrothermal simulation model of SiC MOSFETs to simulate avalanche behavior. The proposed compact MOSFET model includes a parasitic BJT, a body diode, and an intrinsic resistance. The intrinsic resistor represents the decreasing resistance of SiC due to its intrinsic operation in extremely high temperatures. The simulation results of our model accurately reproduce the measurement results of an unclamped inductive switching (UIS) test. According to the simulation results, the main cause of MOSFET failure in the UIS test is that SiC enters intrinsic operation because of the rapid increase of junction temperature over 1200 K.

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“…Studies to understand the limits of avalanche ruggedness in 4H-SiC use 1-D thermal models to estimate the junction temperature [5], calculate threshold voltage reductions [1], as well as perform postfailure device decapsulation [1], [18]- [20]. However, accurate experimental procedures for distinguishing the mechanisms that limit the avalanche current capability of 4H-SiC power MOSFETs have not been presented.…”

Section: Introductionmentioning

confidence: 99%

Analysis of Current Capability of SiC Power MOSFETs Under Avalanche Conditions

Nida

Kakarla

Ziemann

et al. 2021

IEEE Trans. Electron Devices

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The phenomenon of reduced energy capability of power metal-oxide-semiconductor fieldeffect transistors (MOSFETs) at high avalanche currents is investigated in commercial 1.2-kV 4H-SiC MOSFETs. Unclamped inductive switching (UIS) measurements as well as electrical transport simulations are used to identify the current paths and maximum avalanche currents, providing insight into the design limits. The investigated devices show a reduced energy capability for avalanche current above 52 A due to the latching of the parasitic bipolar junction transistor (BJT). The BJT also limits the maximum switchable current to ≤102 A. Based on the measurements and simulations, a procedure utilizing UIS measurements for identification of design limits is presented.

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Robustness of SiC MOSFET under avalanche conditions

Cited by 24 publications

References 8 publications

1.2-kV Vertical GaN Fin-JFETs: High-Temperature Characteristics and Avalanche Capability

1.2-kV Vertical GaN Fin-JFETs: High-Temperature Characteristics and Avalanche Capability

An electrothermal compact model of SiC MOSFETs for analyzing avalanche failure mechanisms

Analysis of Current Capability of SiC Power MOSFETs Under Avalanche Conditions

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