Quantifying self-heating effects with scaling in globally strained Si MOSFETs

Performance Enhancements in Scaled Strained-SiGe pMOSFETs With $ \hbox{HfSiO}_{x}/\hbox{TiSiN}$ Gate Stacks

“…In [10] This reduction may be due self heating arising from the low thermal conductivity of SiGe [40], strain loss with scaling or the increased impact of halo doping on mobility at short gate lengths. One of the dominating factors behind the compromised drain current and transconductance enhancement in scaled strained Si devices fabricated on relaxed SiGe virtual substrates is self heating [41]. The devices in this study comprise of a 40 nm SiGe surface layer on a Si substrate rather than a thin Si layer on a thick SiGe layer, thus the impact of self heating is expected to be considerably lower.…”

Improved Analog Performance in Strained-Si MOSFETs Using the Thickness of the Silicon–Germanium Strain-Relaxed Buffer as a Design Parameter

“…MOSFETs were co-fabricated on the respective wafers through a CMOS process flow. Further details of the MOSFET fabrication process are in [5,12].…”

“…Applying a high frequency drain-source signal suppresses the effect of self heating, hence the intrinsic performance of the MOSFET can be measured. Details of the experimental set up are in the literature [5,[14][15][16]. The measured g DS is integrated with respect to the drain voltage (V DS ) so as to extract the output characteristics.…”

“…The low thermal conductivity SiGe SRB separates the source of heat generation in the channel from the higher thermal conductivity Si substrate which acts as the heat sink. As a result, heat is accumulated in the strained silicon channel layer which gives rise to increased phonon scattering and negative conductance characteristics at high power densities [5,6]. Since the drain current and power density is higher in short channel devices, self-heating increases as the channel length is reduced.…”

The impact of self-heating and SiGe strain-relaxed buffer thickness on the analog performance of strained Si nMOSFETs

“…Conventional graded buffers have thicknesses that are normally on the order of one or several micrometers thick however literature shows that progress has been made on the reduction of buffer thicknesses. Some studies on thin SiGe SRB technology focus on materials growth and characterization [12][13][14] whereas others focus on self-heating in devices [10,11,[15][16][17][18][19][20][21]. The introduction of point defects during the growth of the SRB has been demonstrated as a method of fabricating thin SiGe SRBs [13].…”