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Simultaneous and locally resolved determination of the mechanical stress variation and the free hole concentration using Raman spectroscopy is demonstrated in laser crystallized amorphous silicon layers. Such layers are often used for the fabrication of thin film solar cells, e. g., on borosilicate glass substrates. The combined effects of stress and doping on the Raman signal can be separated based on the use of three wavelengths in the visible. The results show that the free hole concentration in the samples investigated varies between 1 x 10(18) and 1.3 x 10(19) cm(-3). Stress as well as the free hole concentration vary substantially within the sample. The stress level varies between 575 and 850 MPa (+/- 12 MPa). Cross-sectional transmission electron microscopy images show the presence of extended lattice defects such as dislocations and grain boundaries in the crystallized Si layer which could account for the lateral stress variations detected by Raman spectroscopy. The impact of film inhomogeneity in terms of stress and doping on the performance of a solar cell will be discussed. (C) 2010 American Institute of Physics. [doi: 10.1063/1.3319654

We present a 46nm 6F 2 buried word-line (bWL) DRAM technology, enabling the smallest cell size of 0.013um2 published to date. The TiN/ W buried word-line is built below the Si surface, forming a low resistive interconnect and the metal gate of the array transistors. We demonstrate high array device on-current, small parameter variability, high reliability and small parasitic capacitances, resulting in an excellent array performance. The array device can be scaled down to 30nm without compromising its performance.

This work investigates gate leakage mechanisms in advanced strained Si/ SiGe metal-oxide-semiconductor field-effect transistor ͑MOSFET͒ devices. The impact of virtual substrate Ge content, epitaxial material quality, epitaxial layer structure, and device processing on gate oxide leakage characteristics are analyzed in detail. In state of the art MOSFETs, gate oxides are only a few nanometers thick. In order to minimize power consumption, leakage currents through the gate must be controlled. However, modifications to the energy band structure, Ge diffusion due to high temperature processing, and Si/ SiGe material quality may all affect gate oxide leakage in strained Si devices. We show that at high oxide electric fields where gate leakage is dominated by Fowler-Nordheim tunneling, tensile strained Si MOSFETs exhibit lower leakage levels compared with bulk Si devices. This is a direct result of strain-induced splitting of the conduction band states. However, for device operating regimes at lower oxide electric fields Poole-Frenkel emissions contribute to strained Si gate leakage and increase with increasing virtual substrate Ge content. The emissions are shown to predominantly originate from surface roughness generating bulk oxide traps, opposed to Ge diffusion, and can be improved by introducing a high temperature anneal. Gate oxide interface trap density exhibits a dissimilar behavior and is highly sensitive to Ge atoms at the oxidizing surface, degrading with increasing thermal budget. Consequently advanced strained Si/ SiGe devices are inadvertently subject to a potential tradeoff between power consumption ͑gate leakage current͒ and device reliability ͑gate oxide interface quality͒.

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