The impact of self-heating and SiGe strain-relaxed buffer thickness on the analog performance of strained Si nMOSFETs

Alatise, Olayiwola; Kwa, Kelvin S. K.; Olsen, SH; O'Neill, AG

doi:10.1016/j.sse.2009.09.029

Cited by 3 publications

(1 citation statement)

References 36 publications

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“…As discussed in previous sections, a non-destructive, full wafer, high resolution defect metrology would be required to ensure manufacturability control of such approach. From a device point of view, it has to be noted that due to lower thermal conductivity for SiGe relative to Si, self-heating is potentially an important roadblock [18]. A thin SRB would help to alleviate some of the concerns.…”

Section: High Sige % Channel Thru Strain Relaxed Buffer Layer Formationmentioning

confidence: 99%

(Invited) Group IV Epitaxy Applications for Enabling Advanced Device Scaling

et al. 2016

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In this paper, we first review the overall trends for advanced CMOS devices in terms of scalability and performance. To carry on Moore’s law, devices need to be scaled from node to node. To enable this scaling, taller, more rectangular FinFETs with narrower body width at scaled pitches has been demonstrated. However this leads to several key process and integration challenges such as Fin integrity, capacitance increase, channel mobility, sub-fin isolation, and sidewall doping as well as contact resistance reduction. Next, we review the challenges of increasing FinFET device performance (e.g., mobility boost) by using SiGe p-channel FinFET, which has gained quite a lot of attention in the past several years. Several SiGe integration approaches have been reported in the literature, all which are enabled by new epitaxy applications. Consideration of the entire process flow is critical to ensure maximum strain is achieved in the channel with very low defectivity – two critical requirements for High Volume Manufacturing of high performance, low power devices. These topics will be explored for several of the integration approaches mentioned above. Finally, we will discuss the potentially disruptive transition to new device architecture – the Gate-All-Around (GAA) transistor - and discuss new epitaxy opportunities, requirements and challenges for this new device type.

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Section: High Sige % Channel Thru Strain Relaxed Buffer Layer Formationmentioning

confidence: 99%

(Invited) Group IV Epitaxy Applications for Enabling Advanced Device Scaling

et al. 2016

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Non equilibrium entropy generation in nano scale MOSFET transistor based a nonlinear DPL heat conduction model

Echouchene

Mabrouk

2018

2018 9th International Renewable Energy Congress (IREC)

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Effect of Temperature Jump on Nonequilibrium Entropy Generation in a MOSFET Transistor Using Dual-Phase-Lagging Model

Echouchene

Belmabrouk

2017

Journal of Heat Transfer

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This paper investigates the effect of temperature-jump boundary condition on nonequilibrium entropy production under the effect of the dual-phase-lagging (DPL) heat conduction model in a two-dimensional sub-100 nm metal-oxide-semiconductor field effect transistor (MOSFET). The transient DPL model is solved using finite element method. Also, the influences of the governing parameters on global entropy generation for the following cases—(I) constant applied temperature, (II) temperature-jump boundary condition, and (III) a realistic MOSFET with volumetric heat source and adiabatic boundaries—are discussed in detail and depicted graphically. The analysis of our results indicates that entropy generation minimization within a MOSFET can be achieved by using temperature-jump boundary condition and for low values of Knudsen number. A significant reduction of the order of 85% of total entropy production is observed when a temperature-jump boundary condition is adopted.

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The impact of self-heating and SiGe strain-relaxed buffer thickness on the analog performance of strained Si nMOSFETs

Cited by 3 publications

References 36 publications

(Invited) Group IV Epitaxy Applications for Enabling Advanced Device Scaling

(Invited) Group IV Epitaxy Applications for Enabling Advanced Device Scaling

Non equilibrium entropy generation in nano scale MOSFET transistor based a nonlinear DPL heat conduction model

Effect of Temperature Jump on Nonequilibrium Entropy Generation in a MOSFET Transistor Using Dual-Phase-Lagging Model

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