Quantified Impacts of Guardband Reduction on Design Process Outcomes

Abstract

A major source of patterning problems in low-k1 lithography is line-end pullback. Though geometric metrics such as CD at gate edge have served as good indicators, the ever-rising contribution of line-end extension to layout area necessitates reducing pessimism in qualifying line-end patterning. Electrically-aware metrics for line-ends can be helpful in this regard. In this work, we calculate the I on and I o f f impact of line-end taper shapes as well as line-end length. The proposed models are verified using TCAD simulation in a typical 65nm process. We observe that the device threshold voltage is a weak function of line-end pullback, and that the electrical impact of the taper can vary with overlay errors. We apply a non-uniform channel length model in addition to the proposed taper-dependent threshold voltage model to calculate ∆I on and ∆I o f f . Finally, the electrical metric for line-end printing is defined as expected change in I on or I o f f under a given overlay error distribution. We also propose a super-ellipse form to parameterize taper shapes, and then explore a large variety of taper shapes to characterize electrical impact.

Underdesigned and Opportunistic Computing in Presence of Hardware Variability

“…Actual switching power has a weak linear dependence on temperature and its process dependence is also relatively small. Most of the temperature-dependent variation 1 All temperature experiments were conducted in a controlled temperature chamber. Further details can be found in [6] observed is likely due to variation in short-circuit power at lower temperatures and leakage component of active power at higher temperatures.…”

“…Yet hardware designers must accept conservative estimates of hardware specifications and cannot fully leverage software's inherent flexibility and resilience. Guardband for hardware 0278-0070/$31.00 c 2012 IEEE design increases cost-maximizing performance incurs too much area and power overheads [1]. It leaves enormous performance and energy potential untapped as the software assumes lower performance than what a majority of instances of that platform may be capable of most of the time.…”

Impact of Guardband Reduction On Design Outcomes: A Quantitative Approach

“…Therefore, our results suggest that there is justification for the design, EDA and process communities to enable guardband reduction as an economic incentive for manufacturing-friendly design practices. 14 Our future work is in two directions: 1) to assess the impact of RGB on memory embedded designs and 2) to assess the feasibility of simultaneous guardband reduction and voltage lowering to find the best combination of guardband and supply voltage which optimizes for the area, yield, and power.…”

Analytical thermal placement for VLSI lifetime improvement and minimum performance variation

“…• quantification of guardbanding costs, and benefits such as the potential tradeoff of guardband reduction and parametric yield loss for faster design closure and improved random defect yield [2]; • design robustness to variabilities (cf. self-compensation [3]), that include intentional model-to-silicon miscorrelations; and • more rapid process adaptation to design, e.g., through improved understanding of how parametric tests in the fab map through SPICE models to design signoff constraints.…”

“…self-compensation [3]), that include intentional model-to-silicon miscorrelations; and • more rapid process adaptation to design, e.g., through improved understanding of how parametric tests in the fab map through SPICE models to design signoff constraints. 2 …”