Process requirements for continued scaling of CMOS—the need and prospects for atomic-level manipulation

Abstract

Since the advent of the Si-based integrated circuit, ever-increasing function has been available at reduced cost and with reduced consumption of power. This "semiconductor revolution" has been possible because semiconductor devices have the unique feature that as they become smaller they also become faster, consume less power, become cheaper per circuit, and enable more function per unit area of Si. As the basic device approaches atomic dimensions, it is not clear how far scaling can continue, which current processing technologies lack extendibility, and what innovative process technologies will emerge to take their place. Examination of some of the requirements set forth in the International Technology Roadmap for Semiconductors (ITRS) [1] will expose some of the process modules that are likely to limit scaling. Future work that might be developed to meet the needs of the CMOS roadmap will then be initiated. Among the processes being developed for future needs are a range of selflimited growth and etching reactions as well as other process steps that take advantage of atomic-level control and manipulation to enable new classes of substrate materials. The requirements that drive such a level of control, as well as the progress and prospects for these new techniques, are discussed in this paper.

Overview of atomic layer etching in the semiconductor industry

“…However, within die variability remains an ongoing challenge, as it is not always possible to compensate for different layout pattern densities and aspect ratios. 26,27 Compounding this challenge are complicated topographies, multiple patterning schemes, and aspect ratios larger than 60:1. Surface quality is also an unsolved challenge today in continuous etching due to the thick mixed layer.…”

Integrations and challenges of novel high-k gate stacks in advanced CMOS technology

“…Choosing an appropriate processing technique for high-k gate insulator deposition must be investigated since the impact of contamination of high-k precursors and damaged induced by reactive and energetic particles on transistor performance has not yet been completely characterized. The most compatible process is chemical vapor deposition (CVD) or any of its variations which offer a number of benefits, such as good conformality and thickness control, high wafer throughput, and compatible with new 300 nm guidelines [42,43]. Additionally, CVD-based techniques may suffer from poor nucleation characteristics on a bare or H-terminated silicon surface.…”

Limitations of LET in Predicting the Radiation Response of Advanced Devices

“…Polysilicon depletion and quantum tunneling have necessitated the use of metal gates and high-k dielectrics to continue device scaling [20], [21], while the need to reduce series resistance has led to metal silicide and metal clad source and drain regions [22]. Additionally, high-Z materials are used in the backend-of-line (BEOL) of advanced processes in the form of tungsten vias.…”