Polysilicon Interconnection Technology for IC Device

Abstract

A new fabrication technology is presented for short channel Si‐gate MOS‐LSI's. This technology is characterized by two individual phosphorus diffusion processes, the source and drain formation and diffusion into poly‐Si. It is also characterized by using the etching rate difference between phosphorus‐doped and undoped poly‐Si. The former is for decreasing poly‐Si resistance without junction depth dependence, which is effective for high speed MOS‐LSI's with poly‐Si, interconnections. The latter is for precise and uniform patterning of poly‐Si, which is effective for good threshold voltage controllability and uniformity, because they are sensitive to channel length in the range of less than 3 μm. In this paper, technology effects are examined for decreasing poly‐Si resistance by comparison with a conventional process. Also, technology effects are tested for precise and uniform patterning of poly‐Si by threshold voltage distribution of short channel transistors, which are fabricated by this technique. A model of poly‐Si etching profile, considering the edge effect, is presented for precise and uniform patterning mechanism explanation.