Physically-based extraction methodology for accurate MOSFET degradation assessment

Hot Carrier Stress modeling: From degradation kinetics to trap distribution evolution

“…As shown in Fig11, the trap distribution expands in time towards the channel center because of different degradation rates along the interface. This, together with the comparison between the different stress conditions in Fig11, has been qualitatively well addressed in our previous work [18].…”

“…In accordance with [10] and [18], in the first case the drift of Vg at low current Vg CC (Id th =10nA) and of the sub-threshold slope n have been considered, while the drift of Id at high voltage Id CV (Vg th =7V) has been tracked for the mobility aging. Fig8, Fig9 and Fig10 show the experimental and simulated results concerning these parameters.…”

“…A reasonable explanation of this slight disagreement relies on the presence of trapped electrons in the oxide. Indeed, their influence for this technology has been demonstrated to be significant [18], and a fast measurement setup would be required [19]. However, as already highlighted in Section II, for such long stress time, under nominal P/E biases, the Flash cell can be considered "failed", since the programming window is lower than the threshold dispersion.…”

Relaxation-free characterization of Flash programming dynamics along P-E cycling

“…From [8], this behavior is attributed to Coulomb scattering effects linked with HC-induced interface traps (Dit) near the drain. Further investigation will consist in correlating electrical signatures of interface traps both during PROG (saturation regime, as in Figure 7) and during READ operations [9] (linear regime). Fig.…”