Physical Design Automation for 3D Chip Stacks

Abstract

The concept of 3D chip stacks has been advocated by both industry and academia for many years, and hailed as one of the most promising approaches to meet ever-increasing demands for performance, functionality and power consumption going forward. However, a multitude of challenges has thus far obstructed large-scale transition from "classical" 2D chips to stacked 3D chips. We survey major design challenges for 3D chip stacks with particular focus on their implications for physical design. We also derive requirements for advances in design automation, such as the need for a unified workflow. Finally, we outline current promising solutions as well as areas needing further research and development. bly design kit; design standards 2. 3D-CHIP STACKING OPTIONS AND HIGH-LEVEL DESIGN CHALLENGES 3D-chip stacking falls into four categories (Fig. 2): (i) package stacking, (ii) interposer stacks, (iii) through-silicon via (TSV)based 3D ICs, and (iv) monolithic 3D ICs. Each option has its This work is licensed under a Creative Commons Attribution-NonCommercial-ShareAlike International 4.0 License.

Best of both worlds

“…3D integration can be classified into four flavors: (1) through-silicon via (TSV)-based 3D ICs, where chips are fabricated separately and then stacked, with inter-chip connections being realized by TSVs connected to metal layers; (2) face-to-face (F2F) stacking, where two tiers are fabricated separately and then bonded together at their metal faces; (3) monolithic 3D ICs, where multiple tiers are manufactured sequentially, with inter-tier connects based on regular metal vias; (4) 2.5D integration, where chips are fabricated separately and then bonded to a system-level interconnect carrier, the interposer. Each option has its scope, benefits and drawbacks, and requirements for CAD and manufacturing processes [21,27].…”

“…interconnect multiple chips/dies/tiers, thereby promising to overcome the scalability bottleneck ("More-Moore"), which is further exacerbated by challenges for pitch scaling, routing congestion, process variations, et cetera [21,22]. Recent studies and prototypes show that 3D integration can indeed offer significant benefits over conventional 2D chips [23][24][25].…”

3D Integration: Another Dimension Toward Hardware Security

“…3D integration means to stack and interconnect multiple chips or active layers. There are two main drivers for 3D integration [3], [4]: (1) the CMOS scalability bottleneck, which becomes more exacerbated for advanced nodes by issues like routability, pitch scaling, and process variations; and (2) the need to advance means for heterogeneous and system-level integration. Both drivers are also known as (1) "More Moore" and (2) "More than Moore."…”

Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration

“…Successful adoption of 3D chips requires addressing different classical and novel challenges which simultaneously affect the manufacturing processes, design practices and physical design tools [3], [9], [10], [11], [12], [13]. If not properly addressed, these fairly complex challenges (such as adverse coupling effects [14], [15]) may render 3D chips commercially unviable.…”