3D Integration: Another Dimension Toward Hardware Security

Abstract

We review threats and selected schemes concerning hardware security at design and manufacturing time as well as at runtime. We find that 3D integration can serve well to enhance the resilience of different hardware security schemes, but it also requires thoughtful use of the options provided by the umbrella term of 3D integration. Toward enforcing security at runtime, we envision secure 2.5D system-level integration of untrusted chips and "all around" shielding for 3D ICs.

Hardware Security For and Beyond CMOS Technology

“…Still, in [202] it was shown recently that a lateral re-arrangement of the laser setup can suffice to enable such fault-injection attacks also for backside-protected 2D ICs and possibly also for 2.5D and 3D ICs. However, with a dedicated physical design of 3D ICs, e.g., placing TSVs densely at the chip boundaries, forming a "vertical shield" structure [178], along with regular shields in the BEOL and backside protection, even such attacks might remain difficult.…”

“…In Table 1, I summarize selected works; I discuss these and others in some detail next. Note that other papers have reviewed the benefits and fallacies for hardware security arising by 3D and 2.5D integration as well, e.g., see [178][179][180].…”

“…Similar to fault-injection attacks, the notion of physical enclosures enabled by 3D/2.5D integration may hinder read-out and probing attacks. In [178], the authors argued for "all around shields" enabled by 3D ICs. Similar protection against probing has been discussed before in [186,203].…”