Performance analysis of carbon nanotube interconnects for VLSI applications

Srivastava, Navin; Banerjee, Kaustav

doi:10.1109/iccad.2005.1560098

Cited by 194 publications

(187 citation statements)

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“…In order to alleviate such problems, changes in the material used for on-chip interconnections have been sought even in earlier technology generations, for example the transition from aluminum to copper some years back [3]. Carbon nanotubes (CNTs) exhibit a ballistic flow of electrons with electron mean free paths of several micrometers, and are capable of conducting very large current densities [3]. They are therefore proposed as potential candidates for signal and power interconnections [5], [6].…”

Section: Interconnect Challenges In Vlsi Circuitsmentioning

confidence: 99%

“…The steep rise in parasitic resistance of copper interconnects poses serious challenges for interconnect delay [2] (especially at the global level where wires traverse long distances) and for interconnect reliability [4], hence it has a significant impact on the performance and reliability of VLSI circuits. In order to alleviate such problems, changes in the material used for on-chip interconnections have been sought even in earlier technology generations, for example the transition from aluminum to copper some years back [3]. Carbon nanotubes (CNTs) exhibit a ballistic flow of electrons with electron mean free paths of several micrometers, and are capable of conducting very large current densities [3].…”

Section: Interconnect Challenges In Vlsi Circuitsmentioning

confidence: 99%

“…Furthermore, wires, especially power and ground lines, are becoming more and more vulnerable to electromigration because of rapid increases in current densities [2]. The resistance of copper interconnects, with crosssectional dimensions of the order of the mean free path of electrons (~40 nm in Cu at room temperature) in current and imminent technologies [2], is increasing rapidly under the combined effects of enhanced grain boundary scattering, surface scattering and the presence of the highly resistive diffusion barrier layer [3]. The steep rise in parasitic resistance of copper interconnects poses serious challenges for interconnect delay [2] (especially at the global level where wires traverse long distances) and for interconnect reliability [4], hence it has a significant impact on the performance and reliability of VLSI circuits.…”

Section: Interconnect Challenges In Vlsi Circuitsmentioning

confidence: 99%

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Interconnect Challenges and Carbon Nanotube as Interconnect in Nano VLSI Circuits

Fathi¹,

Forouzandeh²

2010

Carbon Nanotubes

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This chapter discusses about the behavior of Carbon Nanotube (CNT) different structures which can be used as interconnect in Very Large Scale (VLSI) circuits in nanoscale regime. Also interconnect challenges in VLSI circuits which lead to use CNT as interconnect instead of Cu, is reviewed. CNTs are classified into three main types including Single-walled Carbon Nanotube (SWCNT), CNT Bundle, and Multi-walled Carbon Nanotube (MWCNT). Because of extremely high quantum resistance of a SWCNT which is about 6.45 kΩ, rope or bundle of CNTs are used which consist of parallel CNTs in order to overcome the high delay time due to the high intrinsic (quantum) resistance. Also MWCNTs which consist of parallel shells, present much less delay time with respect to SWCNTs, for the application as interconnects. In this chapter, first a short discussion about interconnect challenges in VLSI circuits is presented. Then the repeater insertion technique for the delay reduction in the global interconnects will be studied. After that, the parameters and circuit model of a CNT will be discussed. Then a brief review about the different structures of CNT interconnects including CNT bundle and MWCNT will be presented. At the continuation, the time domain behavior of a CNT bundle interconnect in a driver-CNT bundle-load configuration will be discussed and analyzed. In this analysis, CNT bundle is modeled as a transmission line circuit model. At the end, a brief study of stability analysis in CNT interconnects will be presented. Interconnect Challenges in VLSI CircuitsAs interconnect feature sizes shrink, copper resistivity increases due to surface and grain boundary scatterings and also surface roughness [1]. Furthermore, wires, especially power and ground lines, are becoming more and more vulnerable to electromigration because of rapid increases in current densities [2]. The resistance of copper interconnects, with crosssectional dimensions of the order of the mean free path of electrons (~40 nm in Cu at room temperature) in current and imminent technologies [2], is increasing rapidly under the combined effects of enhanced grain boundary scattering, surface scattering and the presence of the highly resistive diffusion barrier layer [3]. The steep rise in parasitic resistance of copper interconnects poses serious challenges for interconnect delay [2]

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Section: Interconnect Challenges In Vlsi Circuitsmentioning

confidence: 99%

Section: Interconnect Challenges In Vlsi Circuitsmentioning

confidence: 99%

Section: Interconnect Challenges In Vlsi Circuitsmentioning

confidence: 99%

See 1 more Smart Citation

Interconnect Challenges and Carbon Nanotube as Interconnect in Nano VLSI Circuits

Fathi¹,

Forouzandeh²

2010

Carbon Nanotubes

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“…Using existing metal interconnects will be highly inefficient and become harder to satisfy the design requirements, such as power, delay, and reliability for future large-scale electronic systems [34,151,152]. This is because as interconnects are scaled due to the increase in the number of components per single chip, their resistance increases.…”

Section: Organization Of the Dissertationmentioning

confidence: 99%

“…Further, the While these links are abstract on purpose, they can nevertheless rather straightforwardly be mapped to actual physical interconnects realized with current technology. Link type 1 corresponds to traditional metal wires, link type 2 to THz wireless links realized by means of carbon nano tubes (CNT) [152], and link type 3 to photonic links [90]. As mentioned above, the energy and throughput values correspond to realistic estimates.…”

Section: Link Type Definitionsmentioning

confidence: 99%

Optimal Network Topologies and Resource Mappings for Heterogeneous Networks-on-Chip

Chung¹

2000

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Communication has become a bottleneck for modern microprocessors and multicore chips because metal wires don't scale. The problem becomes worse as the number of components increases and chips become bigger. Traditional Systemson-Chips (SoCs) interconnect architectures are based on shared-bus communication, which can carry only one communication transaction at a time. This limits the communication bandwidth and scalability. Networks-on-Chip (NoC) were proposed as a promising solution for designing large and complex SoCs. The NoC paradigm provides better scalability and reusability for future SoCs, however, longdistance multi-hop communication through traditional metal wires suffers from both high latency and power consumption. A radical solution to address this challenge is to add long-range, low power, and high-bandwidth single-hop links between distant cores. The use of optical or on-chip RF wireless links has been explored in this context. However, all previous work has focused on regular mesh-based metal wire fabrics that were expanded with one or two additional link types only for long-distance communication.In this thesis we address the following main research questions to address the above-mentioned challenges: (1) What library of different link types would represent an optimum in the design space? (2) How would these links be used to design an application-specific NoC architecture? (3) How would applications use the resulting NoC architecture efficiently? We hypothesize that networks with a higher degree of heterogeneity, i.e., three or more link types, will improve the network throughput and consume less energy compared to traditional NoC architectures.In order to verify our hypothesis and to address the research challenges, we design i and analyze optimal heterogeneous networks under different realistic traffic models by considering different cost and performance trade-offs in a comprehensive technology-agnostic simulation framework that uses metaheuristic optimization techniques. As opposed to related work, our heterogeneous links can be placed anywhere in the network, which allows to explore the entire search space. The resulting application-specific networks are then analyzed by using complex network techniques, such as community detection and small-worldness, to understand how heterogeneous link types are used to improve the NoCs performance and cost.Next, we use the application-specific networks as a target architecture for other applications. The goal is to evaluate the performance of our new NoCs for applications they have not been designed for by finding optimal resource allocations.Our results show that there is an optimal number of heterogeneous link types for each set of constraints and that networks with three or more heterogeneous link types provide significantly higher throughput along with lower energy consumption compared to both homogeneous link type and regular 2D mesh networks under three different traffic scenarios. Our evolved networks with three different technology-driven ...

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Temperature dependant crosstalk analysis in coupled single‐walled carbon nanotube (SWCNT) bundle interconnects

Kumar

Sarkar

2014

Circuit Theory & Apps

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The temperature‐dependent, crosstalk‐induced, noise voltage waveform and its frequency spectrum, in capacitive coupled single‐walled carbon nanotube (SWCNT) bundle interconnects, at the far end of victim line, have been analyzed at 22‐nm technology node. A similar analysis is performed for copper interconnects and a comparison is made between the results of these two analyses. The SPICE simulation results reveal that at temperature variations ranging from 300 to 500 K, compared with conventional metal (copper) conductors, crosstalk noise voltage levels in CNT, at the far end of victim line, are significantly low. Simulated results further reveal that, with rise in interconnect temperatures, compared with copper interconnects, coupled interconnects of SWCNT bundle filter more noise frequency components. Based on these comparative results, an improved model for extracting inter‐bundle, real life, coupling capacitances between SWCNT bundles has been proposed. Copyright © 2014 John Wiley & Sons, Ltd.

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Performance analysis of carbon nanotube interconnects for VLSI applications

Cited by 194 publications

References 30 publications

Interconnect Challenges and Carbon Nanotube as Interconnect in Nano VLSI Circuits

Interconnect Challenges and Carbon Nanotube as Interconnect in Nano VLSI Circuits

Optimal Network Topologies and Resource Mappings for Heterogeneous Networks-on-Chip

Temperature dependant crosstalk analysis in coupled single‐walled carbon nanotube (SWCNT) bundle interconnects

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