2000
DOI: 10.15760/etd.997
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Optimal Network Topologies and Resource Mappings for Heterogeneous Networks-on-Chip

Abstract: Communication has become a bottleneck for modern microprocessors and multicore chips because metal wires don't scale. The problem becomes worse as the number of components increases and chips become bigger. Traditional Systemson-Chips (SoCs) interconnect architectures are based on shared-bus communication, which can carry only one communication transaction at a time. This limits the communication bandwidth and scalability. Networks-on-Chip (NoC) were proposed as a promising solution for designing large and com… Show more

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